US 6,645,818 B1Granted

Method to fabricate dual-metal gate for N- and P-FETs

AssigneeChartered Semiconductor Manufacturing Ltd.

InventorsHo-Chaw Sing, Ng Chit Hwei

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Abstract

A new method for forming a dual-metal gate CMOS transistors is described. An NMOS and a PMOS active area of a semiconductor substrate are separated by isolation regions. A nitride layer is deposited overlying a gate dielectric layer and patterned to form a first dummy gate in each of the active areas. First ions are implanted to form source/drain regions in each of the active areas not covered by the first dummy gates. The first dummy gates are isotropically etched to form second dummy gates thinner than the first dummy gates. Second ions are implanted to form lightly doped source/drain regions in each of the active areas not covered by the second dummy gates. Dielectric spacers are formed on sidewalls of the second dummy gates and the source/drain regions are silicided. The second dummy gates and spacers are removed. A first metal layer is deposited overlying the substrate and patterned to form a first metal gate in one of the NMOS and PMOS active areas. An oxide layer is deposited overlying the substrate and the first metal gate. The oxide layer is polished back to the metal gate. A via is opened through the oxide layer to the substrate in the other one of said NMOS and PMOS areas. A second metal layer is deposited within the via opening and polished back to the oxide layer to form a second metal gate in the other one of the NMOS and PMOS area to complete formation of dual-metal CMOS gates.

Claims32

Dependent claims

A method of forming dual-metal gate CMOS transistors in the fabrication of integrated circuits comprising:

providing an NMOS active area and a PMOS active area of a semiconductor substrate separated by isolation regions;
forming a pad oxide layer overlying said semiconductor substrate in each of said active areas;
depositing a nitride layer overlying said pad oxide layer;
patterning said nitride layer to form a first dummy gate in each of said active areas;
implanting ions to form source/drain regions in each of said active areas not covered by said first dummy gates;
isotropically etching said first dummy gates to form second dummy gates thinner than said first dummy gates;
implanting ions to form lightly doped source/drain regions in each of said active areas not covered by said second dummy gates;
forming dielectric spacers on sidewalls of said second dummy gates;
thereafter siliciding said source/drain regions;
thereafter removing said second dummy gates and said spacers;
depositing a first gate dielectric layer overlying said substrate and said silicided source/drain regions;
depositing a first diffusion barrier layer overlying said first gate dielectric layer;
depositing a first metal layer overlying said first diffusion barrier layer;
patterning said first metal layer, said first diffusion barrier layer, and said first gate dielectric layer to form a first metal gate in one of said NMOS and PMOS active areas;
depositing an oxide layer overlying said substrate and said first metal gate and polishing back said oxide layer to said first metal gate;
opening a via through said oxide layer to said substrate in the other one of said NMOS and PMOS areas;
depositing a second gate dielectric layer within said via;
depositing a second diffusion barrier layer overlying said second gate dielectric layer;
depositing a second metal layer overlying said second diffusion barrier layer and polishing back said second metal layer to said oxide layer to form a second metal gate on said other one of said NMOS and PMOS areas to complete formation of said dual-metal gate CMOS transistors in the fabrication of an integrated circuit.

16 more elements

A method of forming dual-metal gate CMOS transistors in the fabrication of integrated circuits comprising:

providing an NMOS active area and a PMOS active area of a semiconductor substrate separated by isolation regions;
forming a pad oxide layer overlying said semiconductor substrate in each of said active areas;
depositing a nitride layer overlying said pad oxide layer;
patterning said nitride layer to form a first dummy gate in each of said active areas;
implanting first ions to form source/drain regions in each of said active areas not covered by said first dummy gates;
isotropically etching said first dummy gates to form second dummy gates thinner than said first dummy gates;
implanting second ions to form lightly doped source/drain regions in each of said active areas not covered by said second dummy gates;
thereafter driving in said first and second ions in a single rapid thermal annealing step;
forming dielectric spacers on sidewalls of said second dummy gates;
thereafter siliciding said source/drain regions;
thereafter removing said second dummy gates and said spacers;
depositing a first gate dielectric layer overlying said substrate and said silicided source/drain regions;
depositing a first diffusion barrier layer overlying said first gate dielectric layer;
depositing a first metal layer overlying said first diffusion barrier layer;
patterning said first metal layer, said first diffusion barrier layer, and said first gate dielectric layer to form a first metal gate in one of said NMOS and PMOS active areas;
depositing an oxide layer overlying said substrate and said first metal gate and polishing back said oxide layer to said first metal gate;
opening a via through said oxide layer to said substrate in the other one of said NMOS and PMOS areas;
depositing a second gate dielectric layer within said via;
depositing a second diffusion barrier
layer overlying said second gate dielectric layer;
depositing a second metal layer overlying said second diffusion barrier layer and polishing back said second metal layer to said oxide layer to form a second metal gate on said other one of said NMOS and PMOS areas to complete formation of said dual-metal gate CMOS transistors in the fabrication of an integrated circuit.

18 more elements

A method of forming dual-metal gate CMOS transistors in the fabrication of integrated circuits comprising:

providing an NMOS active area and a PMOS active area of a semiconductor substrate separated by isolation regions;
forming a pad oxide layer overlying said semiconductor substrate in each of said active areas;
depositing a nitride layer overlying said pad oxide layer;
patterning said nitride layer to form a first dummy gate in each of said active areas;
implanting first ions to form source/drain regions in each of said active areas not covered by said first dummy gates and driving in said first ions using rapid thermal annealing;
isotropically etching said first dummy gates to form second dummy gates thinner than said first dummy gates;
implanting second ions to form lightly doped source/drain regions in each of said active areas not covered by said second dummy gates and driving in said second ions using a laser annealing;
forming dielectric spacers on sidewalls of said second dummy gates;
thereafter siliciding said source/drain regions;
thereafter removing said second dummy gates and said spacers;
depositing a first gate dielectric layer overlying said substrate and said silicided source/drain regions;
depositing a first diffusion barrier layer overlying said first gate dielectric layer;
depositing a first metal layer overlying said first diffusion barrier layer;
patterning said first metal layer, said first diffusion barrier layer, and said first gate dielectric layer to form a first metal gate in one of said NMOS and PMOS active areas;
depositing an oxide layer overlying said substrate and said first metal gate and polishing back said oxide layer to said first metal gate;
opening a via through said oxide layer to said substrate in the other one of said NMOS and PMOS areas;
depositing a second gate dielectric layer within said via;
depositing a second diffusion barrier
layer overlying said second gate dielectric layer;
depositing a second metal layer overlying said second diffusion barrier layer and polishing back said second metal layer to said oxide layer to form a second metal gate on said other one of said NMOS and PMOS areas to complete formation of said dual-metal gate CMOS transistors in the fabrication of an integrated circuit.

17 more elements

Dependencies are inferred from the claim text.