Method of forming an array of FLASH field effect transistors and circuitry peripheral to such array
AssigneeMicron Technology, Inc.
InventorsRoger W Lindsay, Mark A. Helm
Life of this patent
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Abstract
Thermal oxidation of a peripheral area of a semiconductor substrate is globally restricted with an overlying oxidation resistant layer that is not globally received within the array during formation of a sacrificial oxide layer prior to forming any transistor gate dielectric layer within the array. At least some FLASH field effect transistor gates having floating gate dielectric of a first thickness are formed within the array and at least some non-FLASH field effect transistor gates having gate dielectric of a second thickness are formed within the periphery, with the first and second thicknesses being different. Other aspects and implementations are disclosed.
Claims26
A method forming an array of FLASH field effect transistors and circuitry peripheral to such array, comprising:
- providing a pad oxide over an array area and a periphery area of a semiconductor substrate;
- providing a silicon nitride comprising layer over the pad oxide at least within the periphery area;
- forming a mask over the silicon nitride comprising layer in the periphery area while leaving the array area exposed, and then conducting at least one conductivity modifying implant into the substrate through the pad oxide within the array area using the mask;
- after the conducting, removing the mask;
- and
- after removing the mask, forming at least some FLASH transistor gates within the array area and at least some non-FLASH transistor gates within the periphery area.
A method of forming an array of FLASH field effect transistors and circuitry peripheral to such array, comprising:
- forming a sacrificial masking layer over a pad oxide within an array area and a periphery area of a semiconductor substrate, the sacrificial masking layer being oxide etch resistant;
- forming a mask over the sacrificial masking layer in the periphery area while leaving the sacrificial masking layer in the array area exposed, and then conducting at least one conductivity modifying implant into the substrate through the pad oxide within the array area using the mask;
- using the mask, removing the sacrificial masking layer exposed in the array area while leaving the sacrificial masking layer masked within the periphery area;
- after said removing of the sacrificial masking layer exposed in the array area, removing the mask;
- after removing the mask, etching oxide from the array area, the sacrificial masking layer in the periphery area restricting etching of oxide within the periphery area during said etching;
- and
- after said etching, forming at least some FLASH transistor gates within the array area and at least some non-FLASH transistor gates within the periphery area.
Dependencies are inferred from the claim text.