Process for producing a capacitor configuration

#The invention relates to a process for producing a capacitor configuration.

#In highly integrated memory devices, the information contents of the memory cells are, for example, recorded and provided through the use of appropriate capacitors. During the production of the memory devices or the memory cells on a semiconductor substrate, these capacitors are formed on the semiconductor substrate by using a structuring process and are wired appropriately. In the case of highly integrated circuits, the space required by the individual components, in particular therefore also the space required for the storage capacitors, is a significant factor.

#It has therefore been proposed to form a plurality of substantially mutually independent storage capacitors in relation to an electrode in each case, for example the lower or bottom electrode, to be electrically connected to one another, so that the capacitors connected in this way can be formed physically particularly closely adjacent to one another, since specific contacts or lines can be used jointly and do not have to be formed multiple times. In this case, each capacitor is provided with its lower or bottom electrode on a carrier, on which, at least partly, a dielectric layer is provided, which is then followed, at least partly, by the separately provided upper or top electrodes. In order to develop the concept of the capacitor chain, an appropriate electrical connection has to be provided, for example in relation to the lower or bottom electrodes.

#The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.

#FIG. 1 is a schematic diagram of a basic circuit configuration for a memory device using an embodiment of a capacitor configuration according to the invention produced by the process according to the invention;

#FIG. 2 is a diagrammatic, partial sectional view of a preliminary stage of an embodiment of the capacitor configuration according to the invention using an advantageous mode of the process according to the invention;

#Referring now to the figures of the drawings in detail and first, particularly, to FIG. 1 thereof, there is shown in schematic form, the basic circuit configuration for a memory device 1 having four memory cells S0 to S3, specifically in the form of a chain FeRAM or CFRAM.

#Each of the memory cells S0 to S3 has a ferroelectric capacitor 100-0 to 100-3, which thus form a capacitor configuration according to the invention. Each of the capacitors 100-0, . . . , 100-3 is connected by its terminals a0, b0 to a3, b3 to the source regions or drain regions of corresponding select transistors T0 to T3, whose gate regions make contact with corresponding word lines WL0 to WL3.

#FIG. 1 therefore shows a CFRAM chain having four memory cells S0 to S3. On the input side, this chain is connected via an interconnected chain select transistor or block select transistor BS to the bit line device BL and, on the output side, is connected to a plate line device PL. Through the use of the chain select transistor or block select transistor BS, the respective chain, here including the memory cells S0 to S3, is selected. Within the chain, the individual memory cells S0 to S3 are addressed via the word line devices WL0 to WL3 and the corresponding cell select transistors T0 to T3.