Salicided gate for virtual ground arrays

A method of forming a virtual ground array non-volatile semiconductor memory device, comprising:

• providing a semiconductor substrate having a core region and a peripheral region;
• forming charge trapping layers comprising at least one dielectric layer over the core region;
• forming a poly layer over at least the charge trapping layers;
• patterning the poly layer in the core region thereby forming adjacent word lines without bit line contacts therebetween having a first spacing and forming adjacent word lines with bit line contacts therebetween having a second spacing, the second spacing being wider than the first spacing;
• and
• while at least one of the charge trapping layers covers the bit line contacts, saliciding the word lines.

A method of forming a virtual ground array non-volatile semiconductor memory device, comprising:

• providing a semiconductor substrate, the semiconductor substrate having a core region and a peripheral region;
• forming charge trapping ONO dielectric over the core region;
• forming a poly layer over at least the charge trapping ONO dielectric;
• patterning the poly layer in the core region thereby forming adjacent word lines without bit line contacts therebetween having a first spacing and forming adjacent word lines with bit line contacts therebetween having a second spacing, the second spacing being wider than the first spacing;
• providing one or more salicide protect layers over the core region;
• removing a portion of the one or more salicide protect layers to expose the word lines, without exposing the substrate in the spaces between word lines;
• and
• saliciding the word lines.