Designing method of semiconductor integrated circuit using library storing mask pattern of macro circuit and designing apparatus executing the same

A designing apparatus of a semiconductor integrated circuit, said semiconductor integrated circuit comprising a plurality of macro circuits, said designing apparatus comprising:

• a library storing a macro mask pattern for at least one macro circuit, said at least one macro circuit including:
• an inner circuit outputting an output signal;
• and
• a plurality of buffer circuits, each of which comprises:
• first and second wirings apart from each other;
• a first semiconductor element selectively supplying said first wiring with a power supply potential in accordance with said output signal;
• and
• a second semiconductor element selectively supplying said second wiring with a grounded potential in accordance with said output signal, wherein said macro mask pattern includes a plurality of buffer mask patterns, each of which corresponds to one of said plurality of buffer circuits, each of said plurality of buffer mask patterns comprising:
• a first wiring pattern for said first wiring;
• and
• a second wiring pattern for said second wiring;
• and
• an arrangement wiring tool which selects one of said plurality of buffer circuits as a selected buffer circuit and arranges said macro mask pattern and a third wiring pattern for a third wiring to produce an integrated circuit mask pattern based on said library such that said first and second wiring patterns of said selected buffer circuit are connected with each other by said third wiring pattern.

A computer-readable recording medium recording a library for designing an integrated circuit, said library comprising:

• a macro mask pattern for at least one macro circuit, wherein said at least one macro circuit includes:
• an inner circuit outputting an output signal;
• and
• a plurality of buffer circuits, each of which comprises:
• first and second wirings apart from each other;
• a first semiconductor element selectively supplying said first wiring with a power supply potential in accordance with said output signal;
• and
• a second semiconductor element selectively supplying said second wiring with a grounded potential in accordance with said output signal,
• said macro mask pattern including a plurality of buffer mask patterns, each of which corresponds to one of said plurality of buffer circuits, and each of said plurality of buffer mask patterns comprises:
• a first wiring pattern for said first wiring;
• and
• a second wiring pattern for said second wiring.

A method of designing routing wiring for an integrated circuit, said method comprising:

• providing a macro mask pattern for a macro circuit as a component of said integrated circuit, said macro circuit including:
• an inner circuit outputting an output signal;
• and
• a plurality of patterns for a buffer circuit for said output signal, each said buffer circuit pattern located on a different edge of said macro mask pattern and including an internally-incomplete wiring interconnection, each said pattern being provided with a same set of inputs and potentially providing said output signal as being the corresponding output signal from said macro circuit;
• selecting one of said plurality of patterns of said buffer circuit as being a selected buffer for said output signal, as based on determining a shortest interconnect distance from said output signal of said macro circuit to a subcircuit of said integrated circuit that uses said output signal;
• completing an interconnect for said shortest interconnect distance between said output signal of said macro circuit and said subcircuit that uses said output signal;
• and
• completing the internally-incomplete wiring interconnection of said selected buffer circuit pattern, thereby allowing only said selected buffer to consume electrical power while also providing a shortest interconnect for said output signal from said macro circuit.