Computer-aided design supporting system in which cells can be arranged independently

A computer-aided design supporting method for a semiconductor device comprising:

• providing a cell library which stores a plurality of logic cell patterns, a plurality of power supply cell patterns that are different from each other, and a plurality of ground cell patterns that are different from each other, wherein a logic device pattern of said semiconductor device includes one of said plurality of logic cell patterns, one of said plurality of power supply cell patterns, and one of said plurality of ground cell patterns;
• arranging selected ones of said plurality of logic cell patterns, selected ones of said plurality of power supply cell patterns and selected ones of said plurality of ground cell patterns on cell tracks individually and independently in response to an arrange instruction;
• and
• connection between said selected logic cell patterns, between said selected power supply cell patterns and between said selected ground cell patterns arranged on said cell tracks in response to a wiring instruction to form a pattern of said semiconductor device.

A recording medium which stores a cell library having a plurality of logic patterns, a priority of power supplies cell patterns, and a priority of ground cell patterns, wherein a logic device pattern of said semiconductor device includes one of said priority of logic cell patterns, one of said priority of power supplies cell patterns, and one of said priority of ground cell patterns, and in which program for method is stored, wherein said method comprises:

• arranging selected ones of said plurality of logic cell patterns, selected ones said plurality of power supplies cell patterns and selected ones of said quality of ground cell patterns on cell tracks individually and independently in response to an arranged instruction;
• and
• connecting between said selected logic cell patterns, between selected power supply cell patterns aimed between said selected ground cell patterns arranged on said cell tracks in response to a wiring instruction to form a pattern of said semiconductor device,
• wherein said arranging includes:
• arranging each of said selected logic cell patterns on either of said cell tracks by a logic cell tool in response to a logic cell arrangement instruction;
• arranging each of said selected power supply cell patterns on either of said cell tracks by a power supply cell tool in response to a power supply cell arrangement instruction;
• and
• arranging each of said selected ground cell patterns on either of said cell tracks by a ground cell tool in response to a ground cell arrangement instruction.

A computer-aided design supporting system for a semiconductor device comprising:

• a cell library storing a plurality of logic cell patterns, a plurality of power supply cell patterns, and a plurality of ground cell patterns, wherein a logic device pattern of said select semiconductor device includes one of said plural logic cell patterns, one of said plural of power supply cell patterns, and one of said plural of ground cell patterns;
• an arranging tool which arranges only selected ones of said plural power supply cell patterns in response to an arrange instruction;
• and
• a wiring tool which connects between said selected logic cell patterns, between said selected power supply cell patterns and between said selected ground cell patterns arranged on said cell tracks in response to a wiring instruction to form a pattern of said semiconductor device.