Fully synthesisable and highly area efficient very large scale integration (VLSI) electrostatic discharge (ESD) protection circuit
AssigneeConexant Systems, Inc.
InventorsXiaoming Li, Mark R. Tennyson, Eugene R. Worley
Life of this patent
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Abstract
An electrostatic discharge (ESD) protection circuit comprises a P-channel field effect transistor (PFET), a buffer and a damping network to provide improved protection for an integrated circuit against high-voltage ESD pulses. The ESD protection circuit is capable of being fabricated with a reduced surface area layout to be fully synthesisable with the integrated circuit which it is designed to protect.
Claims22
An electrostatic discharge (ESD) protection circuit, comprising:
- a discharge transistor comprising a single P-channel field effect transistor (PFET) having a source capable of receiving a source voltage at a source input that is susceptible to electrostatic discharge, a drain that is grounded, and a gate capable of receiving either a high voltage to turn off the PFET or a low voltage to turn on the PFET;
- a buffer connected to the gate of the PFET;
- and
- a damping network connected to the buffer.
An electrostatic discharge (ESD) protection circuit, comprising:
- a discharge transistor comprising a single P-channel field effect transistor (PFET) having a source capable of receiving a source voltage at a source input that is susceptible to electrostatic discharge, a drain that is grounded, and a gate capable of receiving either a high voltage to turn off the PFET or a low voltage to turn on the PFET;
- first and second inverters biased by the source input and each having an input and an output, the output of the first inverter connected to the gate of the PFET, the input of the first inverter connected to the output of the second inverter;
- and
- a damping network connected to the input of the second inverter.
An electrostatic discharge (ESD) protection circuit, comprising:
- a discharge transistor comprising a single P-channel field effect transistor (PFET) having a source capable of receiving a source voltage at a source input that is susceptible to electrostatic discharge, a drain that is grounded, and a gate capable of receiving either a high voltage to turn off the PFET or a low voltage to turn on the PFET;
- and
- means for damping the electrostatic discharge at the source input.
Dependencies are inferred from the claim text.