Customizable and programmable cell array

A customizable logic array comprising:

• an array of programmable cells having a multiplicity of inputs and a multiplicity of outputs;
• and
• customized interconnections providing permanent direct interconnections among at least a plurality of said multiplicity of input and at least a plurality of said multiplicity of outputs,
• wherein said customized interconnections use at least three metal layers, wherein at least a majority of said metal layers constitutes repeated subpatterns, wherein at least two of said three metal layers comprise repeated subpatterns, and wherein at least one of said three metal layers comprises a multiplicity of metal laser strips extending parallel to said first axis and also comprises a multiplicity of metal layer strips extending perpendicular to said first axis.

A customizable logic array comprising:

• an array of programmable cells having a multiplicity of inputs and a multiplicity of outputs, each of said programmable cells comprising at least one look-up table;
• and
• customized interconnections providing permanent direct interconnections among at least a plurality of said multiplicity of inputs and at least a plurality of said multiplicity of outputs,
• wherein:
• at least some of said programmable cells are programmable by means of electrical signals supplied thereto;
• at least some of said customized interconnections are customized by lithography carried out in the course of manufacture of said semiconductor customizable logic array;
• and
• said at least one look-up table comprising:
• at least two inputs;
• and
• an electronic circuit which provides high speed response to changes in one of said two inputs with respect to the response time of changes to the other input.

A customizable logic array comprising:

• an array of logic cell having a multiplicity of inputs and a multiplicity of outputs;
• and
• customized interconnections permanently interconnecting at least a plurality of said multiplicity of inputs and at least a plurality of said multiplicity of outputs, wherein each of at least some of said logic cells comprises at least one flip-flop;
• and
• a clock tree providing clock inputs to some of said flip-flops, wherein said clock tree provides a clock tree signal and an inverted clock tree signal, and wherein said clock tree comprises a power saving circuit to allow controlled connection between said clock tree signal and said inverted clock tree signal.

A customizable logic array comprising:

• array of logic cells having a multiplicity of inputs and a multiplicity of outputs;
• at least first, second and third metal layers formed over said array of logic cells, said second metal layer comprising a plurality of generally parallel bands extending parallel to a first axis, each band comprising a multiplicity of second metal layer strips extending perpendicular to said first axis, and said first metal layer comprising a plurality of first metal layer strips extending perpendicular to a second axis;
• and
• at least one via connecting at least one second metal layer strip with said first metal layer, said first metal layer underlying said second metal layer.