High density ROM architecture

A ROM for storing information, including:

• a substrate having a plurality of bit cell regions formed in substrate;
• a plurality of columns of bit lines proximate to the substrate;
• a plurality of rows of word lines proximate to the substrate;
• wherein intersection areas between the plurality of bit lines and the plurality of word lines form nodes which correspond to the plurality of bit cell regions formed in the substrate;
• a first transistor formed in a first bit cell region, which corresponds a first node, wherein a first bit line at the first node is coupled to the first transistor by a first contact;
• a second node wherein a second bit line at the second node is separated from a second bit cell region, which corresponds to the second node, by an insulating layer;
• wherein the second node corresponds to the second bit cell region and to a third bit cell region, wherein the second bit cell region is disposed in the substrate in an area under a first word line and an area under the second bit line, and the third bit cell region is disposed in the substrate in an area under a second word line and an area under the second bit line, wherein the first and second bit cell regions substantially consist of an isolating dielectric material;
• and
• wherein the second bit cell region and the third bit cell region are disposed in the substrate between a first ground region in the substrate and a second ground region in the substrate.

A ROM for storing information, including:

• a substrate having a plurality of bit cell regions formed in substrate;
• a plurality of columns of bit lines disposed proximate to the substrate;
• a plurality of rows of word lines disposed proximate to the substrate;
• wherein intersection areas between the plurality of bit lines and the plurality of the word lines form nodes which correspond to the plurality of bit cell regions formed in the substrate;
• a first bit cell region, which corresponds to a first node, wherein a first transistor is formed in the first bit cell region, and wherein a first bit line at the first node is coupled to the first transistor by a first contact;
• and
• a second bit cell region which corresponds to a second node, wherein the second bit cell region consists substantially of an isolating dielectric material.

A ROM for storing information, including:

• a substrate having a plurality of bit cell regions formed in substrate;
• a plurality of columns of bit lines disposed proximate to the substrate;
• a plurality of rows of word lines disposed proximate to the substrate;
• wherein intersection areas between the plurality of bit lines and the plurality of the word lines form nodes which correspond to the plurality of bit cell regions formed in the substrate;
• a first bit cell region, which corresponds to a first node, wherein a first transistor is formed in the first bit cell region, and wherein a first bit line at the first node is coupled to the first transistor by a first contact;
• a second bit cell region which corresponds to a second node, wherein the second bit cell region consists substantially of an isolating dielectric material;
• wherein the second node corresponds to the second bit cell region and to a third bit cell region, wherein the second bit cell region is disposed in the substrate in an area under a first word line and an area under a second bit line, and the third bit cell region is disposed in the substrate in an area under a second word line and an area under the second bit line, wherein the second and third bit cell regions substantially consist of an isolating dielectric material;
• and
• wherein the second bit cell region and the third bit cell region are disposed in a substrate between a first ground region in the substrate and a second ground region in the substrate.