Circuit structure with a parasitic transistor having high threshold voltage

A circuit structure integrated in a semiconductor substrate and comprising:

• at least one pair of transistors each formed in a respective active area region,
• wherein each transistor has a source region and a drain region and a channel region intervening between said source and drain regions being overlaid by a gate region,
• the gate regions of the pair of transistors are connected electrically together by an overlying conductive layer and respective contacts, the contacts between the gate regions and the conductive layer are formed above the active areas,
• each gate region comprises a first portion formed in a first polysilicon layer, a second portion partly overlapping said first portion and formed in a dielectric layer, and a third portion formed in a second polysilicon layer, and
• said first and third portions are short-circuited.

An information handling system including at least one circuit structure integrated in a semiconductor substrate and comprising:

• at least one pair of transistors each formed in a respective active area region;
• and
• an isolation oxide region between the active area regions of the pair of transistors,
• wherein each transistor has a source region and a drain region and a channel region intervening between said source and drain regions being overlaid by a gate region,
• the gate regions of the pair of transistors are connected electrically together by an overlying conductive layer and respective contacts between the gate regions and the conductive layer, the contacts between the gate regions and the conductive layer each being formed directly above one of the active area regions,
• each gate region comprises a first portion formed in a first polysilicon layer, a second portion partly overlapping said first portion and formed in a dielectric layer, and a third portion formed in a second polysilicon layer, and
• said first and third portions are short-circuited.

An information handling system including a circuit structure integrated in a semiconductor substrate and comprising:

• at least one pair of transistors each formed in a respective active area region,
• wherein each transistor has a source region and a drain region and a channel region intervening between said source and drain regions being overlaid by a gate region;
• the gate regions of the pair of transistors are connected electrically together by an overlying conductive layer and respective contacts,
• the contacts between the gate regions and the conductive layer are formed above the active areas,
• each gate region comprises a first portion formed in a first polysilicon layer, a second portion partly overlapping said first portion and formed in a dielectric layer, and a third portion formed in a second polysilicon layer, and
• said first and third portions are short-circuited.

A circuit structure integrated in a semiconductor substrate and comprising:

• at least one pair of transistors each formed in a respective active area region,
• wherein each transistor has a source region and a drain region and a channel region intervening between said source and drain regions being overlaid by a gate region,
• the channel regions of the pair of transistors are both the same conductivity type,
• the gate regions of the pair of transistors are connected electrically together by an overlying conductive layer and respective contacts between tie gate regions and the conductive layer, the contacts between the gate regions and the conductive layer each being formed directly above one of the active area regions,
• each gate region comprises a first portion formed in a first polysilicon layer, a second portion partly overlapping said first portion and formed in a dielectric layer, and a third portion formed in a second polysilicon layer, and
• said first and third portions are short-circuited.