Method of reducing the extrinsic body resistance in a silicon-on-insulator body contacted MOSFET

Abstract

As the silicon-on-insulator field effect transistor (SOI FET) CMOS technology continues migrating towards thinner SOI thicknesses to reduce the parasitic capacitance and improve the short channel effects, it is known that the body resistance of body contacted MOSFETs increases correspondingly. The problem is compounded for strong halo and weak wells device designs for T-shaped or L-shaped BC-MOSFETs. The invention provides a structure and a method that includes an additional well level implant for n-type and p-type devices in selected parts of the extended gate region. A new mask increases the channel doping at the extended gate region to prevent that region from fully depleting and increasing the carrier concentration for lower resistance. Since the physical gate dimensions are usually narrower than the mask dimensions, the mask is slightly offset from the extended gate edge to avoid excessive encroachment into the intrinsic device channel region. The SOI FET includes: a pattern having a first extended region to form a gate for the SOI FET, and a second extended region to isolate the body contact region from the SOI FET; a first sub-region under the first extended region having added doping to adjust the threshold voltage of the SOI FET, the first sub-region defining a gate width of the SOI FET; a second sub-region under the second extended region and an adjoining portion of the first extended gate region to form a low resistance extrinsic body contact region; source and drain regions respectively positioned at each side of the first extended region; and a body contact region adjacent to the second extended region opposite to the SOI FET.

Dependencies are inferred from the claim text.