Method for forming interconnection structure in an integration circuit
AssigneeMacronix International Co., Ltd.
InventorHenry Chung
Life of this patent
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Abstract
A method for fabricating vias and trenches in a dual-damascene multilevel interconnection structure of an integration circuit is provided. The method uses chemical vapor deposition and flowfill dielectric technology to deposit a dielectric material at low temperature for fabricating interconnection structure in an integration circuit. It comprises the following steps: (a) forming photo-resist patterns; (b) depositing a dielectric layer at low temperature by chemical vapor deposition and flowfill dielectric technologies; (c) removing the dielectric layer by chemical-mechanical polishing to expose the photo-resist patterns; (d) removing the photo-resist patterns by chemical-mechanical polishing; and (e) stabilizing the dielectric layer by thermal curing.
Claims9
A method for fabricating interconnection structure in an integration circuit comprising the steps of:
- forming photo-resist patterns by providing a substrate and depositing a photo-resist layer on said substrate;
- depositing a dielectric layer at a temperature of approximately 40° C. by chemical vapor deposition;
- removing said dielectric layer by chemical-mechanical polishing to remove the portion of said dielectric layer that covers said photo-resist patterns and to expose said photo-resist patterns;
- removing said exposed photo-resist patterns;
- and
- curing said dielectric layer.
A method for fabricating dual-damascene multilevel interconnection structure comprising the steps of:
- providing a substrate with a first metal conductor layer and a first inter-metal dielectric layer deposited thereon and a first barrier metal layer being formed between said first metal conductor layer and said first inter-metal dielectric layer;
- forming a first barrier dielectric layer on the top surface of said substrate to cover said first metal conductor layer, said first inter-metal dielectric layer and said first barrier metal layer;
- forming via patterns using a method comprising the steps of:
- forming a layer of photo-resist via patterns by coating photo-resist on the surface of said first barrier dielectric layer;
- depositing a second dielectric layer;
- removing said second dielectric layer by chemical-mechanical polishing to remove the portion of said second dielectric layer that covers said photo-resist via patterns and to expose said photo-resist via patterns;
- removing said exposed photo-resist via patterns;
- and
- curing said second dielectric layer by thermal curing;
- forming trench patterns;
- and
- filling a second metal conductor layer.
Dependencies are inferred from the claim text.