Cmos of semiconductor device and method for manufacturing the same

A method for manufacturing a complementary metal oxide semiconductor (CMOS) device, comprising:

• forming a photo resist film pattern on a semiconductor substrate including a gate insulation film, the photo resist film exposing a p-well region of a cell and an n-well region of a peripheral circuit region;
• forming a first metal layer having a work function ranging from 4.8 to 5.0 eV on the entire surface of the semiconductor substrate;
• removing the photo resist film pattern to expose the p-well region of the peripheral circuit region including the gate insulation film;
• sequentially forming a polysilicon layer and a second metal layer on the entire surface of the semiconductor substrate;
• forming a first gate electrode having a stacked structure of a first metal layer pattern, a polysilicon layer pattern, and a second metal layer pattern on the p-well of the cell region and the n-well of the peripheral circuit region, and simultaneously forming a second gate electrode having a stacked structure of the polysilicon layer pattern, a second metal layer pattern on a p-well of a peripheral circuit region by etching the first metal layer, the second metal layer and the polysilicon layer via a photolithography process using a gate electrode mask;
• and
• forming an n-type source/drain region by ion-implanting n-type impurities into the P-well;
• and
• forming a p-type source/drain region by ion-implanting p-type impurities into the n-well.