Method for high temperature oxidations to prevent oxide edge peeling
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsChing-Shan Lu, Kuo-Bin Huang, Jih-Churng Twu
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Abstract
A method for preventing oxide layer peeling in a high temperature annealing process including providing a plurality of spaced apart stacked semiconductor wafers for carrying out a high temperature annealing process including ambient nitrogen gas the plurality of spaced apart stacked semiconductor wafers stacked such that a process surface including an oxide layer of at least one semiconductor wafer is adjacent to a backside surface of another semiconductor wafer said backside surface having a layer of silicon nitride formed thereon prior to carrying out the high temperature annealing process; and, carrying out the high temperature annealing process.
Claims19
A method for preventing oxide layer peeling in a high temperature oxide layer annealing process comprising the steps of:
- providing a plurality of spaced apart stacked semiconductor wafers for carrying out a high temperature oxide layer annealing process including ambient nitrogen gas the plurality of spaced apart stacked semiconductor wafers stacked such that a process surface including the oxide layer of at least one semiconductor wafer is positioned adjacent to a backside surface of a control wafer said backside surface having a layer of silicon nitride formed thereon prior to carrying out the high temperature annealing process;
- and,
- carrying out the high temperature oxide layer annealing process.
A method for preventing silicon oxide layer peeling in a high temperature silicon oxide layer annealing process comprising the steps of:
- providing a plurality of spaced apart stacked semiconductor wafers for carrying out a high temperature silicon oxide layer annealing process including ambient nitrogen gas the plurality of spaced apart stacked semiconductor wafers stacked such that at least one semiconductor wafer having a process surface including the silicon oxide layer formed thereon is adjacently disposed to a backside surface of an adjacently disposed semiconductor wafer said backside surface having a layer of silicon nitride formed thereon prior to carrying out the high temperature silicon oxide layer annealing process;
- and,
- annealing the silicon oxide layer at a temperature above about 900 degrees Centigrade.
Dependencies are inferred from the claim text.