Non-volatile memory device having self-aligned gate structure and method of manufacturing same

A method for manufacturing a non-volatile memory device comprising:

• forming field regions extending in one direction on a semiconductor substrate to define active regions;
• forming a tunnel dielectric layer on the active regions;
• forming first floating gate patterns extending in the direction of the length of the field regions;
• forming mold patterns on the first floating gate patterns crossing the first floating gate patterns and selectively exposing predetermined portions of the first floating gate patterns;
• forming floating gates by removing the exposed portions of the first floating gate patterns using the mold patterns as a mask;
• forming interlayer dielectric layer patterns for insulating the floating gates from one another by filling gaps between the mold patterns;
• removing the mold patterns exposed between the interlayer dielectric layer patterns using the interlayer dielectric layer patterns as an etching mask;
• forming a dielectric layer on the floating gates exposed by the removal of the mold patterns between the interlayer dielectric layer patterns;
• and
• forming control gates aligned with the floating gates and crossing the field region.

A method for manufacturing a non-volatile memory device comprising:

• forming field regions extending in one direction on a semiconductor substrate to define active regions;
• forming a tunnel dielectric layer on the active regions;
• forming first floating gate patterns covering the tunnel dielectric layer and extending in the direction of the length of the field regions;
• forming mold patterns on the first floating gate patterns crossing the first floating gate patterns and selectively exposing predetermined portions of the first floating gate patterns;
• forming floating gates by removing the exposed portions of the first floating gate patterns using the mold patterns as a mask;
• forming interlayer dielectric layer patterns for insulating the floating gates from one another by filling gaps between the mold patterns;
• removing the mold patterns exposed between the interlayer dielectric layer patterns using the interlayer dielectric layer patterns as an etching mask;
• forming a dielectric layer on the floating gates exposed by the removal of the mold patterns between the interlayer dielectric layer patterns;
• forming a conductive polysilicon layer along the entire surface of the structure including the dielectric layer, but not completely filling gaps between the interlayer dielectric layer patterns;
• forming a metal layer on the conductive polysilicon layer, filling the gaps between the interlayer dielectric layer patterns;
• and
• forming control gates, each consisting of the conductive polysilicon layer and the metal layer, in the gaps between the interlayer dielectric layer patterns, self-aligned with the floating gates, by planarizing the metal layer and the conductive polysilicon layer to expose the top surfaces of the interlayer dielectric layer patterns.

A method for manufacturing a non-volatile memory device comprising:

• forming a tunnel dielectric layer on a semiconductor substrate;
• forming first floating gate patterns on the tunnel dielectric layer;
• forming mold patterns on the first floating gate patterns to selectively expose predetermined portions of the first floating gate patterns;
• forming floating gates by removing the exposed portions of the first floating gate patterns using the mold patterns as a mask;
• forming interlayer dielectric layer patterns for insulating the floating gates from one another by filling gaps between the mold patterns;
• removing the mold patterns exposed between the interlayer dielectric layer patterns using the interlayer dielectric layer patterns as an etching mask;
• forming a dielectric layer on the floating gates exposed by the removal of the mold patterns between the interlayer dielectric layer patterns;
• forming a conductive polysilicon layer pattern in the gaps between the interlayer dielectric layer patterns on the dielectric layer;
• and
• forming control gates, each consisting of the conductive polysilicon pattern and a metal layer pattern, aligned with the floating gates, by forming the metal layer pattern to be aligned with the conductive layer pattern.

A method for manufacturing a non-volatile memory device comprising:

• forming a tunnel dielectric layer on a semiconductor substrate;
• forming first floating gate patterns on the tunnel dielectric layer;
• forming mold patterns on the first floating gate patterns to selectively expose predetermined portions of the first floating gate patterns;
• forming floating gates by removing the exposed portions of the first floating gate patterns using the mold patterns as a mask;
• forming interlayer dielectric layer patterns for insulating the floating gates from one another by filling gaps between the mold patterns;
• removing the mold patterns exposed between the interlayer dielectric layer patterns using the interlayer dielectric layer patterns as an etching mask;
• forming a dielectric layer on the floating gates exposed by the removal of the mold patterns between the interlayer dielectric layer patterns;
• forming a conductive polysilicon layer pattern in the gaps between the interlayer dielectric layer patterns on the dielectric layer;
• and
• forming control gates, each consisting of the conductive polysilicon layer pattern and a metal silicide layer, aligned with the floating gates, by forming the metal silicide layer on the top surface of the conductive polysilicon layer pattern.

A method for manufacturing a non-volatile memory device comprising:

• forming a tunnel dielectric layer on a semiconductor substrate;
• forming first floating gate patterns on the tunnel dielectric layer;
• forming mold patterns on the first floating gate patterns to selectively expose predetermined portions of the first floating gate patterns;
• forming floating gates by removing the exposed portions of the floating gates using the mold patterns as a mask;
• forming interlayer dielectric layer patterns for insulating the floating gates from one another by filling gaps between the mold patterns;
• removing the mold patterns exposed between the interlayer dielectric layer patterns using the interlayer dielectric layer patterns as an etching mask;
• forming a dielectric layer on the floating gates exposed by the removal of the mold patterns between the interlayer dielectric layer patterns;
• forming a conductive polysilicon layer pattern in the gaps between the interlayer dielectric layer patterns on the dielectric layer;
• forming control gates, each consisting of the conductive polysilicon layer pattern and a metal silicide layer, aligned with the floating gates, by forming the metal silicide layer on the top surface of the conductive polysilicon layer pattern;
• forming a contact hole to expose a predetermined portion of the semiconductor substrate by selectively etching the interlayer dielectric layer patterns;
• forming a conductive polysilicon contact filling the contact hole;
• and
• forming a metal silicide contact on the top surface of the conductive polysilicon contact by silicidating the top portion of the conductive polysilicon contact when forming the metal silicide layer.