US 6,639,301 B2Granted

Semiconductor device and manufacturing method thereof

AssigneeSanken Electric Co., Ltd.

InventorHideyuki Andoh

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Abstract

A semiconductor device embraces an n-type first semiconductor region, defined by first and second end surfaces and a first outer surface connecting the first and second end surfaces; a p-type second semiconductor region, defined by third and fourth end surfaces and a second outer surface connecting the third and fourth end surfaces, the fourth end surface is in contact with the first end surface; an n-type third semiconductor region connected with the first semiconductor region at the second end surface; a p-type fourth semiconductor region connected with the second semiconductor region at the third end surface; and a fifth semiconductor region having inner surface in contact with the first and second outer surfaces and an impurity concentration lower than the first semiconductor region. The fifth semiconductor region surrounds the first and second semiconductor regions and is disposed between the third and fourth semiconductor regions.

Claims14

Dependent claims

A semiconductor device comprising:

a first semiconductor region of a first conductivity type, defined by a first end surface, a second end surface opposing to the first end surface and a first outer surface connecting the first and second end surfaces;
a second semiconductor region of a second conductivity type, defined by a third end surface, a fourth end surface opposing to the third end surface and a second outer surface connecting the third and fourth end surfaces, the fourth end surface being in contact with the first end surface;
a third semiconductor region of the first conductivity type having an impurity concentration higher than the first semiconductor region connected with the first semiconductor region at the second end surface, the perimeter of the third semiconductor region serving as a part of the chip outer surface;
a fourth semiconductor region of the second conductivity type connected with the second semiconductor region at the third end surface, the perimeter of the fourth semiconductor region serving as another part of the chip outer surface so that a pn junction interface between the third and fourth semiconductor regions terminates at the chip outer surface;
and
a fifth semiconductor region having an inner surface in contact with the first and second outer surfaces and an impurity concentration lower than the first semiconductor region, configured such that the fifth semiconductor region surrounds the first and second semiconductor regions, the fifth semiconductor region being disposed between the third and fourth semiconductor regions.

3 more elements

A semiconductor device terminating a pn junction interface at a chip outer surface comprising:

a first semiconductor region of a first conductivity type, defined by a first end surface, a second end surface opposing to the first end surface and a first outer surface connecting the first and second end surfaces;
a second semiconductor region of the second conductivity type, defined by a third end surface, a fourth end surface opposing to the third end surface and a second outer surface connecting the third and fourth end surfaces, the fourth end surface being in contact with the first end surface;
a third semiconductor region of the first conductivity type having an impurity concentration higher than the first semiconductor region connected with the first semiconductor region at the second end surface, the perimeter of the third semiconductor region serving as a part of the chip outer surface;
a fourth semiconductor region of the second conductivity type connected with an upper part of the second outer surface near the third end surface, the perimeter of the fourth semiconductor region serving as another part of the chip outer surface so that a pn junction interface between the third and fourth semiconductor regions terminates at the chip outer surface;
and
a fifth semiconductor region having an inner surface in contact with the first and second outer surfaces and an impurity concentration lower than the first semiconductor region, configured such that the fifth semiconductor region surrounds the first and second semiconductor regions, the fifth semiconductor region being disposed between the third and fourth semiconductor regions.

3 more elements

Dependencies are inferred from the claim text.