Method and apparatus for reducing process-induced charge buildup
AssigneeArtisan Components, Inc.
InventorAli Akbar Iranmanesh
Life of this patent
Estimating the term…
Abstract
Method and apparatus are disclosed for protection of a circuit against process-induced electrical discharge. The method includes forming a diode in close proximity to a charge collector structure capable of exhibiting the antenna effect, and connecting the diode to the charge collector structure by means of local interconnect techniques during the intermediate processing steps. Additionally, the diode may be formed beneath a connecting pad to educe or eliminate antenna effect problems without significant loss of a die area.
Claims6
Apparatus for preventing gate oxide damage in a CMOS circuit by dissipating process-induced charge comprising:
- a substrate of a first conductivity type having an active area of second conductivity type fabricated therein;
- a well of the second conductivity formed within the substrate, such that the well and the substrate cooperate to act as a diode;
- an insulating layer formed above the substrate, the well and the active area, the insulating layer subsequently being removed from the well;
- and
- a polysilicon layer formed directly over the insulating layer overlying the active area and the well to define a polysilicon structure of the second conductivity type, the polysilicon structure extending between the active area to at least a portion of the well.
Apparatus for preventing gate oxide damage in a CMOS circuit comprising:
- a substrate of a first conductivity having an active area of second conductivity;
- a well of a second conductivity formed within the substrate, such that the well and the substrate cooperate to act as a diode;
- an insulating layer formed above the substrate and the active area;
- a polysilicon layer formed directly over the insulating layer and the well to define a polysilicon structure of the second conductivity, the polysilicon structure extending between the insulating layer overlying the active area to at least a portion of the well;
- and
- a connecting pad located over the polysilicon layer overlying the well of the second conductivity.
Dependencies are inferred from the claim text.