Non-volatile memory cell

A non-volatile memory comprising:

• a substrate of a first conductivity type,
• a plurality of non-volatile memory cells, with each memory cell comprising a MOS transistor having a ring arrangement in said substrate and comprising
• a central diffusion region of a second conductivity type in said substrate at a center of the ring arrangement for defining a center electrode;
• a floating date surrounding said center electrode;
• a peripheral diffusion region of the second conductivity type in said substrate along a periphery of the ring arrangement for defining at least one per peripheral electrode;
• and
• said center electrode, said floating gate and said at least one peripheral electrode being arranged so that programming is performed by applying a first voltage reference to said center electrode and a second voltage reference to said at least one peripheral electrode so that capacitive coupling with said floating gate causes a charge to be injected therein.

An integrated circuit comprising:

• at least one non-volatile memory comprising a plurality of non-volatile memory cells, each memory cell comprising at least one MOS transistor having a ring arrangement and comprising
• a center electrode at a center of the ring arrangement;
• a floating gate surrounding said center electrode;
• at least one peripheral electrode along a periphery of the ring arrangement;
• and
• said center electrode, said floating gate and said at least one peripheral electrode being arranged so that programming is performed by applying a first voltage reference to said center electrode and a second voltage reference to said at least one peripheral electrode so that capacitive coupling with said floating gate causes a charge to be injected therein.

A method for making a non-volatile memory cell comprising at least one MOS transistor having a ring arrangement, the method comprising:

• forming a central diffusion region in a semiconductor layer at a center of the ring arrangement for defining a center electrode;
• forming a floating date surrounding the center electrode;
• forming a peripheral diffusion region in the semiconductor layer along a periphery of the ring arrangement for defining at least one peripheral electrode;
• and
• the center electrode, the floating gate and the at least one peripheral electrode being arranged so that programming is perform by applying a first voltage reference to the center electrode and a second voltage reference to the at least one peripheral electrode so that capacitive coupling with the floating gate causes a charge to be injected therein.