US 6,638,854 B2Granted

Semiconductor device and method for manufacturing the same

AssigneeHitachi, Ltd.

InventorsYoshio Homma, Seiichi Kondo, Noriyuki Sakuma, Naofumi Ohashi, Toshinori Imai, Hizuru Yamaguchi, Nobuo Owada

Life of this patent

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Abstract

In order to suppress an increase of depressions, etc. to occur on a copper based alloy layer during polishing when a copper based alloy inlaid wiring is formed with the damascene method in grooves formed in an insulating film, the polishing rate for the lower metallic layer is set not less than five times faster than the etching rate for the same and the polishing rate for the insulating film is set lower than the polishing rate for the lower metallic layer when the upper metallic layer 13 to become a wiring and the lower metallic layer 12 to become a barrier are polished respectively. Thus, the object damascene wiring can be formed with less erosion on each of insulating layers and dishing on each of metallic layers respectively.

Claims16

Dependent claims

A method for manufacturing a semiconductor device, comprising the steps of:

forming a first insulator on a semiconductor substrate;
forming a plug connecting to a semiconductor substrate in said first insulator;
forming a second insulator over said plug and over said first insulator;
forming a first groove in the second insulator;
forming a first conductor film on the first groove and on the second insulator;
forming a second conductor film on the first conductor film;
polishing said second conductor film using an abrasive free polishing agent comprising of an organic acid, an inhibitor, and an oxidizer;
polishing said first conductor film and remaining second conductor film using polishing agent including abrasives and an inhibitor which concentration is lower than said inhibitor;
forming a third insulator over said second insulator and planarizing said third insulator;
forming a first etching stopper film on said third insulator and forming a fourth insulator on said first etching stopper film;
forming a via in said third insulator and a groove in said fourth insulator;
forming a third conductor film on said via and groove, and over said fourth insulator;
forming a fourth conductor film on said third conductor film;
polishing said fourth film using polishing agent including abrasives and a BTA of a first concentration;
and
polishing said third conductor film using polishing agent including abrasives and a BTA of a second concentration which is larger than said first concentration.

13 more elements

Dependencies are inferred from the claim text.

Facts

Application: 10/227,284Filed 26 Aug 2002 · continuation
Priority: JP 10-3172339 Nov 1998
Published: US 2003/0003713 A12 Jan 2003
Granted: 28 Oct 2003
Term ends: Not estimatedThe source records don’t support an estimate.

Classification6 codes

H10P 52/403
Chemomechanical polishing [CMP]: of conductive or resistive materials
C09G 1/02
Polishing compositions: containing abrasives or grinding agents
H10W 20/062
Of conductive parts of the interconnections: by smoothing of conductive parts, e.g. by planarisation
H10P
Generic processes or apparatus for the manufacture or treatment of devices covered

Family

Application09/361,989Parent of this division · filed 28 Jul 1999
Application09/978,068Parent of this continuation · filed 17 Oct 2001
US 2003/0003713 A1Pre-grant publication · published 2 Jan 2003
Application09/978,068Parent of this division
US 6,326,299 B1Parent of this division
US 2002/0025605 A1Published application
US 6,638,854 B2This patent

From the US filing history. Foreign family members aren’t listed.