Method for manufacturing semiconductor devices having copper interconnect and low-K dielectric layer

Abstract

A dual damascene process for forming semiconductor devices containing a copper interconnect and a low-K dielectric layer on a wafer which allows the copper interconnect to be formed subsequent to the formation of the low-K dielectric layer while preventing the low-K dielectric layer from being degraded by a subsequent plasma etching. The process includes the main steps of: (a) forming a silica glass layer on a wafer surface, which contains an inter-level dielectric (IDL) layer; (b) photolithographically patterning the silica glass layer according to the pattern intended for the copper interconnect; (c) conformably depositing a spacer dielectric layer on the silica glass layer; (d) anisotropically etching the spacer dielectric layer to form a sidewall spacer; (e) depositing a low-K dielectric material on the wafer to form a low-K dielectric layer, covering the silica glass layer and the sidewall spacer, followed by planarizing the low-dielectric layer by chemical-mechanical polishing; (f) photolithographically removing the silica glass layer to form a trench in the low-K dielectric layer; (g) depositing a copper layer to fill the trench; and (h) planarizing the copper layer.

Dependencies are inferred from the claim text.