Method for reducing gate length bias
AssigneeUnited Microelectronics Corp.
InventorsKai-Jen Ko, Yuan-Li Tsai, Ming-Hui Wu, Steven Huang, Ching-Chun Hwang
Life of this patent
Estimating the term…
Abstract
A method for reducing a gate length bias is disclosed. The method utilizes an additional blanket ion implantation process to adjust the etching property of the undoped conductive layer. According to the present invention, a polysilicon layer is used to form NMOS and PMOS gate electrodes so that the gate length bias between the NMOS gate electrodes and the PMOS gate electrodes can be effectively reduced.
Claims21
A method for reducing a gate length bias, said method comprising:
- providing a substrate having a P well and an N well therein and an undoped conductive layer thereon;
- performing an N type blanket ion implantation process on said conductive layer to form a lightly doped conductive layer;
- performing an N type ion implantation process on the portion of said lightly doped conductive layer over said P well to form a heavily doped conductive layer by using an implantation mask covering the portion of said lightly doped conductive layer over said N well, wherein the dosage of said blanket ion implantation process is smaller than the dosage of said ion implantation process;
- and
- defining said heavily doped conductive layer and said lightly doped conductive layer separately to form an NMOS gate electrode and a PMOS gate electrode.
A method for reducing a gate length bias, said method comprising:
- providing a substrate having a P well and an N well therein and an undoped polysilicon layer thereon;
- performing an N type blanket ion implantation process on said polysilicon layer to form a lightly doped polysilicon layer;
- performing an N type ion implantation process on the portion of said lightly doped polysilicon layer over said P well to form a heavily doped polysilicon layer by using an implantation mask covering the portion of said lightly doped polysilicon layer over said N well, wherein the dosage of said blanket ion implantation process is smaller than the dosage of said ion implantation process by about one order of magnitude;
- and defining said heavily doped polysilicon layer and said lightly doped polysilicon layer separately to form an NMOS gate electrode and a PMOS gate electrode.
A method for reducing a gate length bias, said method comprising:
- providing a P type silicon substrate having a P well and an N well therein and an undoped polysilicon layer thereon;
- performing an N type blanket ion implantation process with dopants of phosphorus ions on said polysilicon layer to form a lightly doped polysilicon layer;
- performing an N type ion implantation process with dopants of phosphorus ions on the portion of said lightly doped polysilicon layer over said P well to form a heavily doped polysilicon layer by using an implantation mask covering the portion of said lightly doped polysilicon layer over said N well, wherein the dosage of said blanket ion implantation process is smaller than the dosage of said ion implantation process by about one order of magnitude;
- and
- defining said heavily doped polysilicon layer and said lightly doped polysilicon layer separately to form an NMOS gate electrode and a PMOS gate electrode.
Dependencies are inferred from the claim text.