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US 6,638,816 B2Granted
Integrated circuit device with MIM capacitance circuit and method of manufacturing the same
AssigneeNEC Electronics Corporation
InventorMasaru Wakabayashi
Life of this patent
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Abstract
A first conductive layer of metal silicide, a silicon layer, an insulating layer, and a second conductive layer of metal or metal silicide are deposited in the order named on a surface of a a semiconductor substrate. Thereafter, the second conductive layer and the insulating layer are patterned to expose the silicon layer. The exposed silicon layer and the first conductive layer are patterned, thereby forming an MIM capacitance circuit.
Claims8
A method of manufacturing an integrated circuit device, comprising the steps of:
- forming a first conductive layer of metal silicide on a surface of a semiconductor substrate;
- forming a silicon layer on a surface of said first conductive layer;
- forming an insulating layer on a surface of said silicon layer;
- forming a second conductive layer of metal or metal silicide on a surface of said insulating layer;
- patterning said second conductive layer and said insulating layer to expose said silicon layer;
- patterning the exposed silicon layer and said first conductive layer to form an MIM capacitance circuit;
- and
- removing a portion of said exposed silicon layer of said MIM capacitance circuit where said insulating layer is deposited non-simultaneously with removal of a thin oxide film used in forming another element on said semiconductor substrate.
5 more elements
Dependencies are inferred from the claim text.