Formation of self-aligned vertical connector
AssigneeInternational Business Machines Corporation
InventorsGary Bela Bronner, Ramachandra Divakaruni
Life of this patent
Estimating the term…
Abstract
In a vertical-transistor based semiconductor structure, the problem of making a reliable electrical connection between the node of the deep trench capacitor and the lower electrode of the vertical transistor is solved by; depositing a sacrificial insulator layer, forming a vertical hardmask on the inner trench walls above the sacrificial insulator, then stripping the insulator to expose the substrate walls; diffusing dopant into the substrate walls to form a self-aligned extension of the buried strap; depositing the final gate insulator; and then forming the upper portion of the vertical transistor.
Claims19
A method of making an electrical connection between a lower electrical contact and a contact region of a semiconductor substrate comprising the steps of:
- forming said lower electrical contact having a contact top surface at a reference depth in an aperture formed in a semiconductor substrate and having aperture sidewalls;
- forming a first sidewall layer overlapping said lower electrical contact along a vertical axis;
- forming a vertical hardmask on said aperture sidewalls above said reference depth;
- recessing an upper portion of said lower electrical contact to a second depth below said reference depth;
- recessing an upper portion of said sidewall layer adjacent to said lower electrical contact below said reference depth, thereby exposing said aperture sidewalls below said vertical hardmask in a diffusion window;
- depositing supplementary conductive material in said diffusion window to the level of said second depth, thereby establishing said diffusion window between said second depth and said vertical hardmask;
- and
- diffusing dopant into the substrate walls through said diffusion window, thereby forming a conductive path vertically through said substrate from said lower electrode to said contact region of said substrate.
A method of making an electrical connection between a lower electrical contact and a contact region of a semiconductor substrate having a pad oxide layer, comprising the steps of:
- a) forming an aperture having aperture sidewalls in said substrate;
- b) forming said lower electrical contact having a contact top surface at a reference depth in said aperture;
- c) forming a first sidewall layer on said aperture sidewalls overlapping said lower electrical contact along a vertical axis;
- d) recessing an upper portion of said lower electrical contact and said sidewall layer adjacent to said lower electrical contact below said reference depth, thereby exposing said aperture sidewalls below said reference depth;
- e) depositing conductive material adjacent to said exposed aperture sidewalls to the level of said reference depth;
- f) forming a vertical hardmask on the aperture sidewalls above said reference depth;
- g) recessing an upper portion of said lower electrical contact to a second depth below said reference depth, thereby establishing a diffusion window between said reference depth and said vertical hardmask;
- h) diffusing dopant into the substrate walls through said diffusion window, thereby forming a conductive path vertically from said lower electrode to said contact region of a semiconductor substrate:
- and performing a divot replacement step further comprising filling an undercut below said pad oxide with nitride.
Dependencies are inferred from the claim text.