US 6,638,799 B2Granted

Method for manufacturing a semiconductor device having a silicon on insulator substrate

AssigneeMatsushita Electric Industrial Co., Ltd.

InventorNaoki Kotani

Life of this patent

Estimating the term…

Abstract

In a method for manufacturing a MIS type SOI device, when an ion-implantation is carried out to form pocket regions of an n-type MISFET, an ion-implantation mask having a mask opening and covering a body contact region of a p-type MISFET is applied, and when an ion-implantation is carried out to form pocket regions of a p-type MISFET, an ion-implantation mask having a mask opening and covering a body contact region of an n-type MISFET is applied. By preventing the impurities of the conductivity type opposite to that of the body contact region from being introduced into the pathway portion, the body electrical potential can be securely fixed.

Claims3

Dependent claims

A method for manufacturing a semiconductor device, said semiconductor device comprising a first MISFET and a second MISFET:

said first MISFET having:
a gate electrode formed on a semiconductor layer of an SOI substrate;
source/drain regions of a first conductivity type formed in both regions beside said gate electrode in said semiconductor layer;
a well region of a second conductivity type formed below said gate electrode in said semiconductor layer;
pocket regions doped with impurities of said second conductivity type at a higher concentration than that of said well region and formed between said well region and said source/drain regions in said semiconductor layer;
a body contact region doped with impurities of said second conductivity type at a higher concentration than that of said well region and connected to said well region;
a pathway portion doped with impurities of said second conductivity type and connecting said well region and said body contact region;
said second MISFET having:
said gate electrode formed on said semiconductor layer of said SOI substrate;
source/drain regions of said second conductivity type formed in both regions beside said gate electrode in said semiconductor layer;
a well region of said first conductivity type formed below said gate electrode in said semiconductor layer;
pocket regions doped with impurities of said first conductivity type at a higher concentration than that of said well region and formed between said well region and said source/drain regions in said semiconductor layer;
a body contact region doped with impurities of said first conductivity type at a higher concentration than that of said well region connected to said well region;
a pathway portion doped with impurities of said first conductivity type and connecting said well region and said body contact region;
said method comprising:
a pocket ion-implantation step for implanting impurity ions of said second conductivity type into said pocket regions of said first MISFET by using a first ion-implantation mask, which has an opening in an active region on said first MISFET and which includes said body contact region of said second MISFET, covering said second MISFET forming region, and implanting impurity ions of said first conductivity type into said pocket regions of said second MISFET by using a second ion-implantation mask, which has an opening in an active region of said second MISFET and which includes said body contact region of said first MISFET, covering said first MISFET forming region.

13 more elements

Dependencies are inferred from the claim text.

patentgrep

Loading patent…

Abstract

A method for manufacturing a semiconductor device, said semiconductor device comprising a first MISFET and a second MISFET:

said first MISFET having:
a gate electrode formed on a semiconductor layer of an SOI substrate;
source/drain regions of a first conductivity type formed in both regions beside said gate electrode in said semiconductor layer;
a well region of a second conductivity type formed below said gate electrode in said semiconductor layer;
pocket regions doped with impurities of said second conductivity type at a higher concentration than that of said well region and formed between said well region and said source/drain regions in said semiconductor layer;
a body contact region doped with impurities of said second conductivity type at a higher concentration than that of said well region and connected to said well region;
a pathway portion doped with impurities of said second conductivity type and connecting said well region and said body contact region;
said second MISFET having:
said gate electrode formed on said semiconductor layer of said SOI substrate;
source/drain regions of said second conductivity type formed in both regions beside said gate electrode in said semiconductor layer;
a well region of said first conductivity type formed below said gate electrode in said semiconductor layer;
pocket regions doped with impurities of said first conductivity type at a higher concentration than that of said well region and formed between said well region and said source/drain regions in said semiconductor layer;
a body contact region doped with impurities of said first conductivity type at a higher concentration than that of said well region connected to said well region;
a pathway portion doped with impurities of said first conductivity type and connecting said well region and said body contact region;
said method comprising:
a pocket ion-implantation step for implanting impurity ions of said second conductivity type into said pocket regions of said first MISFET by using a first ion-implantation mask, which has an opening in an active region on said first MISFET and which includes said body contact region of said second MISFET, covering said second MISFET forming region, and implanting impurity ions of said first conductivity type into said pocket regions of said second MISFET by using a second ion-implantation mask, which has an opening in an active region of said second MISFET and which includes said body contact region of said first MISFET, covering said first MISFET forming region.

13 more elements