Semiconductor integrated circuit and its fabrication method
AssigneeHitachi, Ltd.
InventorsMichiaki Nakayama, Masato Hamamoto, Kazutaka Mori, Satoru Isomura
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AssigneeHitachi, Ltd.
InventorsMichiaki Nakayama, Masato Hamamoto, Kazutaka Mori, Satoru Isomura
Estimating the term…
An integrated circuit having a CMOS circuit constituted by electrically connecting an n-type well 2, in which p-channel transistor Tp of the CMOS circuit is set, with a supply line Vdd through switching transistor Tps, and electrically connecting a p-type well 3, in which n-channel transistor Tn of the CMOS circuit is set, with supply line Vss through switching transistor Tns. Thermal runaway due to leakage current can be controlled by turning off switching transistors Tps and Tns and supplying potentials suitable for a test to the n-type well 2 and the p-type well 3 from an external unit when the integrated circuit is being tested. Fluctuations of the latch-up phenomenon and operation speed can be prevented by turning on switching transistors Tps and Tns and setting the n-type well 2 and the p-type well 3 to the voltages Vdd and Vss, respectively.
A method for fabricating a semiconductor integrated circuit device, the method comprising:
Dependencies are inferred from the claim text.