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US 6,635,937 B2Granted
Semiconductor integrated circuit device
AssigneeHitachi, Ltd.
InventorsFumio Ootsuka, Yusuke Nonaka, Satoshi Shimamoto, Sohei Omori, Hideto Kazama
Life of this patent
Estimating the term…
Abstract
To improve performance, a capacitor is provided between storage nodes of an SRAM and a device having an analog capacitor on a single substrate, a plug is formed in a silicon oxide film on a pair of n channel type MISFETs in a memory cell forming area, and a local wiring LIc for connecting respective gate electrodes and drains of the pair of n channel type MISFETs is formed over the silicon oxide film and the plug. Thereafter, a capacitive insulating film and an upper electrode are formed over the local wiring LIc.
Claims23
A semiconductor integrated circuit device having a memory cell including a pair of n channel type MISFETs having gate electrodes and drains respectively cross-connected with each other, comprising:
- an interlayer insulating film formed over the pair of n channel type MISFETs;
- a pair of conductive layers formed such that one of the pair of the conductive layers electrically connects a gate electrode of one of the pair of n channel type MISFETs and the drain of another of the pair of n channel type MISFETs and such that another one of the pair of the conductive layers electrically connects a gate electrode of another one of the pair of n channel type MISFETs and the drain of one of the pair of n channel type MISFETs;
- a capacitive insulating film formed on the pair of conductive layers and including an opening provided on one of the pair of conductive layers;
- and
- an upper electrode formed on the capacitive insulating film and the opening,
- wherein the interlayer insulating film includes a first insulating film formed on the pair of n channel type MISFETs and a second insulating film formed on the first insulating film,
- wherein contact holes are formed in the first insulating film, and wiring trenches are formed in the second insulating film, and
- wherein said conductive layers respectively include connecting portions embedded in the contact holes and local wirings embedded in the wiring trenches.
5 more elements
A semiconductor integrated circuit device having a memory cell including a pair of n channel type MISFETs having gate electrodes and drains respectively cross-connected with each other, comprising:
- an interlayer insulating film formed over the pair of n channel type MISFETs;
- a pair of conductive layers formed such that one of the pair of the conductive layers electrically connects the gate electrode of one of the pair of n channel type MISFETs and the drain of another of the pair of n channel type MISFETs and such that another one of the pair of the conductive layers electrically connects a gate electrode of another one of the pair of n channel type MISFETs and the drain of one of the pair of n channel type MISFETs, said respective conductive layers being formed within trenches defined in the interlayer insulating film;
- a capacitive insulating film formed on the pair of conductive layers and including an opening provided on one of the pair of conductive layers;
- and
- an upper electrode formed on the capacitive insulating film and the opening,
- wherein the interlayer insulating film includes a first insulating film formed on the pair of n channel type MISFETs and a second insulating film formed on the first insulating film,
- wherein contact holes are formed in the first insulating film, and wiring trenches are formed in the second insulating film, and
- wherein said conductive layers respectively include connecting portions embedded in the contact holes and local wirings embedded in the wiring trenches.
5 more elements
A semiconductor integrated circuit device having a memory cell including a pair of n channel type MISFETs having gate electrodes and drains respectively cross-connected with each other, comprising:
- an interlayer insulating film formed over the pair of n channel type MISFETs;
- a pair of conductive layers formed such that one of the pair of the conductive layers electrically connects the gate electrode of one of the pair of n channel type MISFETs and the drain of another of the pair of n channel type MISFETs and such that another one of the pair of the conductive layers electrically connects a gate electrode of another one of the pair of n channel type MISFETs and the drain of one of the pair of n channel type MISFETs;
- said respective conductive layers being formed within trenches defined in the interlayer insulating film, and including upper portions having protrusions which protrude from the surface of the interlayer insulating film;
- a capacitive insulating film formed on the interlayer insulating film including the surfaces of the respective protrusions of the pair of conductive layers, said capacitive insulating film having an opening provided on one of the pair of conductive layers;
- and
- an upper electrode formed on the capacitive insulating film and the opening,
- wherein the interlayer insulating film includes a first insulating film formed on the pair of n channel type MISFETs and a second insulating film formed on the first insulating film,
- wherein contact holes are formed in the first insulating film, and wiring trenches are formed in the second insulating film, and
- wherein said conductive layers respectively include connecting portions embedded in the contact holes and local wirings embedded in the wiring trenches.
6 more elements
A semiconductor integrated circuit device comprising:
- a memory cell formed on a first area;
- and
- a capacitor element fanned on a second area;
- the memory cell including a pair of n channel type MISFETs having gate electrodes and drains respectively cross-connected with each other,
- an interlayer insulating film formed over the pair of n channel MISFETs,
- a pair of first conductive layers formed such that one of the pair of first conductive layers electrically connects the gate electrode of one of the pair of n channel type MISFETs and the drain of another of the pair of n channel type MISFETs and such that another of the pair of first conductive layers electrically connects the gate electrode of another of the pair of n channel type MISFETs and the drain of one of the pair of n channel type MISFETs,
- a first capacitive insulating film formed on the pair of first conductive layers and including an opening provided on one of the pair of first conductive layers,
- a first upper electrode formed on the first capacitive insulating film and the opening,
- the interlayer insulating film formed so as to extend to said second area,
- a second conductive layer formed on the interlayer insulating film,
- a second capacitive insulating film formed on the second conductive layer,
- a second upper electrode formed on the second capacitive insulating film,
- wherein the first and second conductive layers, the first and second capacitive insulating films and the first and second upper electrodes are respectively formed in the same layer.
10 more elements
A semiconductor integrated circuit device comprising:
- a memory cell formed on a first area;
- and
- a capacitor element formed on a second area,
- the memory cell including a pair of n channel type MISFETs having gate electrodes and drains respectively cross-connected with each other, an interlayer insulating film formed on the pair of n channel MISFETs,
- a pair of first conductive layers formed such that one of the pair of first conductive layers electrically connects the gate electrode of one of the pair of n channel type MISFETs and the drain of another of the pair of n channel type MISFETs and such that another of the pair of first conductive layers electrically connects the gate electrode of another of the pair of n channel type MISFETs and the drain of one of the pair of n channel type MISFETs, respective ones of the pair of first conductive layers being formed within trenches defined in the interlayer insulating film and including upper electrodes having protrusions which protrude from the surface of the interlayer insulating film, a first capacitive insulating film formed on the interlayer insulating film including the surfaces of the respective protrusions of the pair of first conductive layers and including an opening provided on one of the pair of first conductive layers,
- a first upper electrode formed on the first capacitive insulating film and the opening,
- the interlayer insulating film formed so as to extend to said second area,
- a second conductive layer formed within trenches defined in the interlayer insulating film and including an upper portion having a protrusion which protrudes from the surface of the interlayer insulating film,
- a second capacitive insulating film formed on the interlayer insulating film including the surface of the protrusion of the second conductive layer,
- a second upper electrode formed on the second capacitive insulating film, wherein the first and second conductive layers, the first and second capacitive insulating films and the first and second upper electrodes are respectively formed in the same layer.
7 more elements
A semiconductor integrated circuit device comprising:
- a memory cell formed on a first area;
- and
- a capacitor element formed on a second area,
- the memory cell including a pair of n channel type MISFETs having gate electrodes and drains respectively cross-connected with each other,
- an interlayer insulating film formed over the pair of n channel MISFETs,
- a pair of first conductive layers formed such that one of the pair of first conductive layers electrically connects the gate electrode of one of the pair of n channel type MISFETs and the drain of another of the pair of n channel type MISFETs and such that another of the pair of first conductive layers electrically connects the gate electrode of another of the pair of n channel type MISFETs and the drain of one of the pair of n channel type MISFETs, respective ones of the pair of first conductive layers being formed within trenches defined in the interlayer insulating film,
- a first capacitive insulating film formed on the pair of first conductive layers and including an opening provided on one of the pair of first conductive layers,
- a first upper electrode formed on the first capacitive insulating film and the opening,
- the interlayer insulating film formed so as to extend to said second area,
- a second conductive layer formed within trenches defined in the interlayer insulating film,
- a second capacitive insulating film formed on the second conductive layer,
- a second upper electrode formed on the second capacitive insulating film, wherein the first and second conductive layers, the first and second capacitive insulating films and the first and second upper electrodes are respectively formed in the same layer.
9 more elements
Dependencies are inferred from the claim text.