SRAM layout for relaxing mechanical stress in shallow trench isolation technology

An SRAM device with a preferred layout having source/drain regions formed in active areas, a pair of parallel wordline conductors and a contact to said source/drain regions, said device comprising:

• said source/drain regions being formed in a doped silicon semiconductor substrate with 90° transitions in the profile of the active areas with respect to said layout in critical locations where a said source/drain region is formed,
• said active areas having double back patterns crossing said wordline conductors at right angles thereto, with said double back patterns including transverse regions of said active areas parallel to said parallel wordline conductors located between said parallel wordline conductors where said active areas cross said parallel wordline conductors,
• a dielectric layer formed above said active areas,
• mesas formed in said silicon substrate between STI trench isolation regions with said mesas having edges, said STI trench isolation regions being filled with STI isolation material,
• said mesas being separated by said STI isolation material which is covered with the dielectric layer and with said dielectric layer covering edges of said mesas,
• at least one of said wordline conductors being composed of doped polysilicon formed above said active areas transverse to said active area,
• with a source/drain region formed in said critical locations in said active areas juxtaposed with at least one of said wordline conductors,
• said source/drain regions having sidewalls being formed along the <100> crystal plane with respect to said layout, and
• said contact to said source/drain region extending down through said dielectric layer to said source/drain region. with said contact being aligned with said mesas and isolated from a <110> silicon (Si) plane of said substrate by the STI isolation material and the dielectric layer.

An SRAM device having a doped semiconductor substrate with STI trench isolation regions in said substrate filled with STI isolation material, with a preferred layout having source regions and drain regions formed in active areas, wordline conductors and contacts comprising:

• mesas formed in said semiconductor substrate between said STI trench isolation regions, said active areas being formed in a doped silicon semiconductor substrate with 90° transitions in the profile of the active area in critical locations with respect to said layout where source regions are to be formed,
• a dielectric layer formed above said active areas,
• said mesas being separated by the STI isolation material which is covered with the dielectric layer and with said dielectric layer covering edges of said mesas,
• at least one of said wordline conductors being composed of doped polysilicon formed above said active areas transverse to said active areas,
• with source regions formed in said critical locations in said active areas juxtaposed with at least one of said wordline conductors to form pass gate transistors with drain regions in said active areas juxtaposed with at least one of said wordline conductors on the opposite side from said source regions to form pass gate transistors and with said active are as having double back patterns where,said active areas cross said wordline conductors,
• said source regions having sidewalls,
• said sidewalls of said source regions being formed along a <100> crystal plane with respect to said layout,
• each of said contacts to said source regions and said drain regions is formed adjacent to at least one of said wordline conductors extending down through said dielectric layer to at least one of said source regions and at least one of said drain regions respectively, said contacts being aligned with said mesas and isolated from a <110> silicon (Si) plane of said substrate by the STI isolation material and the dielectric layer, and
• said source regions and said drain regions having similar sizes and shapes.

A semiconductor SRAM device having source regions, drain regions formed in active areas, a pair of parallel wordline conductors and contacts comprising:

• the active areas being formed in a doped semiconductor substrate with a layout with 90° transitions in the profile of at least one of the active areas in critical locations where source regions are to be formed,
• mesas formed in the silicon substrate between STI trench isolation regions filled with STI isolation material,
• said active areas having double back patterns crossing said pair of parallel wordline conductors at right angles thereto, with said double back patterns including transverse regions of said active areas parallel to said pair of parallel wordline conductors located between said pair of parallel wordline conductors where said active areas cross said pair of parallel wordline conductors,
• a dielectric layer formed above active areas,
• the mesas being separated by the STI isolation material which is covered with the dielectric layer and with said dielectric layer covering edges of said mesas,
• the contacts being aligned with the mesas and isolated from the substrate by the STI isolation material and the dielectric layer, and
• the contacts to the drain regions being formed extending down from at least one of said pair of parallel wordline conductors through the dielectric layer to the drain regions.