Semiconductor device cell having regularly sized and arranged features
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorHiroshi Makino
Life of this patent
Estimating the term…
Abstract
In a semiconductor device, first gate electrodes contributing to transistor operations and second gate electrodes not contributing to the transistor operations each have the same gate length, share the common gate length direction, and are arranged in the same pitch. The first gate electrodes and the second gate electrodes are all made to extend, in the gate width direction, beyond the longest active region width. With such a configuration, it is possible to provide a semiconductor device having a pattern structure that will not cause performance degradation of transistors when designing a semiconductor integrated circuit within a semiconductor device.
Claims15
A semiconductor device, comprising:
- a transistor forming region having a plurality of source/drain regions formed on a semiconductor substrate, and a plurality of gate electrodes arranged in a first direction, each having a gate width direction that matches a second direction orthogonal to said first direction;
- and
- a plurality of field effect transistors each formed of one of said plurality of gate electrodes and two of said plurality of source/drain regions;
- said plurality of field effect transistors having at least two kinds of such field effect transistors that are different in active region widths corresponding to lengths along the second direction of said plurality of source/drain regions, and each gate width of said plurality of gate electrodes being made at least equal to a longest one of said active region widths.
A semiconductor device, characterized in that a semiconductor integrated circuit is formed by arranging a plurality of integrated circuits in rows and columns, each integrated circuit including
- a transistor forming region having a plurality of source/drain regions formed on a semiconductor substrate, and a plurality of gate electrodes arranged in a first direction, each having a gate width direction that matches a second direction orthogonal to said first direction, and
- a plurality of field effect transistors each formed of one of said plurality of gate electrodes and two of said plurality of source/drain regions,
- said plurality of field effect transistors having at least two kinds of such field effect transistors that are different in active region widths corresponding to lengths along the second direction of said plurality of source/drain regions, and each gate width of said plurality of gate electrodes being made at least equal to a longest one of the active region widths.
Dependencies are inferred from the claim text.