Semiconductor device and method of manufacturing the same
AssigneeSanyo Electric Co., Ltd.
InventorsToshimitsu Taniguchi, Takashi Arai, Masashige Aoyama
Life of this patent
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Abstract
A P-channel type DMOS transistor includes heavily doped source/drain layers 12 formed in an N-type well 2, a gate electrode 18 formed on a channel layer located between the source/drain layers 12, an N-type body layer 14 formed in the vicinity of the source layer, and a lightly-doped drain layer 6 formed between the channel layer and the drain layer 12. In such a P-channel type DMOS transistor, a P-type layer 16 is formed in the channel layer at the upper part of the N-type body layer 14. In this configuration, the driving capability of the P-channel type DMOS transistor can be improved.
Claims8
A semiconductor device comprising:
- a semiconductor layer having a first conduction type;
- source/drain layers having a second conduction type which is opposite to said first conduction type;
- a gate electrode formed on a channel layer located between the source/drain layers;
- a body layer having the first conduction type formed at least below the gate electrode;
- and
- a layer having the second conduction type formed in the channel layer between the entire upper part of the body layer having the first conduction type and the gate electrode, and separated from the semiconductor layer by the body layer.
A semiconductor device comprising:
- a semiconductor layer having a first conduction type;
- source/drain layers having a second conduction type which is opposite to the first conduction type;
- a gate electrode formed on a channel layer located between the source/drain layers;
- a layer having the second conduction type formed in the channel layer;
- and
- a body layer having the first conduction type formed at least below the gate electrode and below an entire lower surface of the layer having the second conduction type.
Dependencies are inferred from the claim text.