Method of fabricating borderless contact using graded-stair etch stop layers

The creation of a borderless contact holes to source and drain regions of a CMOS device, comprising the steps of:

• providing a semiconductor surface, at least one gate electrode having been provided over said semiconductor surface, said at least one gate electrode having been provided with points of electrical contact to source and drain regions that are self-aligned with said at least one gate electrode;
• consecutively depositing over said semiconductor surface including exposed surfaces of said at least one gate electrode a first layer of dielectric over which a second layer of dielectric is deposited over which a third layer of dielectric is deposited, said first layer of dielectric having an etch selectivity which is high when compared with an etch selectivity of said second layer of dielectric, said third layer of dielectric having an etch selectivity which is high when compared with an etch selectivity of said second layer of dielectric;
• patterning and etching said third and said second layer of dielectric, creating at least one opening through said third and said second layers of dielectric that aligns with said point of electrical contact to a source region of said at least one gate electrode, further creating at least one opening through said third and said second layers of dielectric that aligns with said point of electrical contact to a drain region of said at least one gate electrode;
• depositing a layer fourth layer of dielectric over said third layer of dielectric, including inside surfaces of said least one opening through said third and said second layers of dielectric, said fourth layer of dielectric being deposited to a thickness between about 5,000 and 15,000 Angstrom;
• patterning and etching said fourth layer of dielectric, creating at least one opening through said fourth layer of dielectric that aligns with said at least one opening created through said third and said second layers of dielectric, exposing said first least of dielectric inside said at least one opening created through said third and said second layers of dielectric;
• and
• etching said exposed surface of said first layer of dielectric, creating at least one opening through said fourth, third, second and first layers of dielectric that aligns with said point of electrical contact to a source region of said at least one gate electrode, further creating at least one opening through said fourth, third, second and first layers of dielectric that aligns with said point of electrical contact to a drain region of said at least one gate electrode, substantially removing said exposed first layer of dielectric from a bottom surface of said at least one opening through said fourth, third, second and first layers of dielectric, leaving in place a measurable amount of said first layer of dielectric around a perimeter of a bottom surface of said opening created through said fourth, third, second and first layers of dielectric, creating a graded lower profile of said at least one opening created through said fourth, third, second and first layers of dielectric whereby a diameter of said at least one opening created through said fourth, third, second and first layers of dielectric decreases by a measurable amount when proceeding from said fourth layer of dielectric to said third layer of dielectric to said second layer of dielectric to said first layer of dielectric.