Method of producing alignment marks

A method of producing alignment marks in a structure with integrated circuits, which comprises the following method steps:

• forming a first metal layer over a semiconductor substrate with integrated circuits, the first metal layer having a thickness and a surface;
• applying an insulator layer on the first metal layer, the insulator layer having a thickness significantly greater than the thickness of the first metal layer;
• etching contact holes and alignment trenches into the insulator layer, the contact holes and the alignment trenches in each case opening out at the first metal layer and the alignment trenches having widths significantly greater than widths of the contact holes;
• introducing metal into the alignment trenches and the contact holes and subsequently treating surface of the insulator layer with chemical mechanical polishing, wherein metal areas within the alignment trenches and the contact holes form polished top sides, the metal areas are lowered in a region of the alignment trenches and form profiles for the alignment marks;
• and
• subsequently depositing a second metal layer on the insulator layer and on the top sides of the metal areas within the alignment trenches and the contact holes, whereby local depressions are formed on a top side of the second metal layer in the region of the alignment trenches in accordance with the respective profiles, and wherein the depressions form alignment marks.