Method for fabricating a bipolar transistor and method for fabricating an integrated circuit configuration having such a bipolar transistor

A method of fabricating a bipolar transistor, which comprises:

• producing a collector doped by a first conductivity type in a substrate of semiconductor material;
• producing a first insulating layer covering the collector on the substrate;
• producing a polysilicon layer doped by a second conductivity type, opposite the first conductivity type, on the first insulating layer;
• producing a second insulating layer on the polysilicon layer;
• forming a first depression above the collector, cutting through the second insulating layer and the polysilicon layer;
• subsequently producing a first auxiliary layer and a second auxiliary layer above the first auxiliary layer, and forming the first and second auxiliary layers so thin as not to fill the first depression;
• anisotropically etching the second auxiliary layer until the first auxiliary layer is uncovered;
• isotropically etching the first auxiliary layer selectively with respect to the second auxiliary layer until a part of the first insulating layer is uncovered;
• removing a part of the first insulating layer by isotropic etching selectively with respect to the first auxiliary layer, thereby uncovering parts of the polysilicon layer and parts of the collector;
• replacing the removed part of the first insulating layer with a base by selective epitaxy of silicon in situ-doped by the second conductivity type;
• subsequent to producing the base, producing a third auxiliary layer;
• producing spacers in the first depression on the third auxiliary layer, by deposition and etching-back of material;
• isotropically etching the third auxiliary layer selectively with respect to the spacers, and uncovering the base;
• depositing polysilicon doped by the first conductivity type and, thereabove, an isolating layer, and jointly patterning to produce an emitter covered by the isolating layer, partly arranged in the first depression, adjoining the base, and partly overlapping the second insulating layer;
• anisotropically etching the second insulating layer selectively with respect to the isolating layer until the polysilicon layer is uncovered;
• producing a silicide layer on the polysilicon layer but not on the isolating layer;
• producing a base contact on the silicide layer;
• and
• subsequent to producing the silicide layer, at least partly removing the isolating layer, and producing an emitter contact on the emitter.