Method for annealing using partial absorber layer exposed to radiant energy and article made with partial absorber layer

Abstract

A method of the invention comprises forming a partial absorber layer (PAL) over at least one integrated transistor device formed on a semiconductor substrate, and exposing the PAL to radiant energy. A first portion of the radiant energy passes through the PAL and is absorbed in the source and drain regions adjacent a gate region of the integrated transistor device and in the semiconductor substrate underneath the field isolation regions of the integrated device. A second portion of the radiant energy is absorbed by the PAL and is thermally conducted from the PAL to the source and drain regions. The first and second portions of the radiant energy are sufficient to melt the source and drain regions to anneal the junctions of the integrated device. The first portion of radiant energy traveling to the substrate underneath the field isolation regions is insufficient in fluence to melt the substrate, and the second portion of radiant energy absorbed by PAL over the field isolation regions is insufficient to cause ablation or surface damage. Accordingly, the source and drain regions can be melted for annealing without overheating the PAL overlying or the substrate beneath the field isolation regions. The invention also includes an article including an integrated device made with a PAL.

Dependencies are inferred from the claim text.