US 6,635,539 B2 · Method for fabricating a MOS transistor using a self-aligned silicide technique

Abstract

A method for fabricating a MOS transistor using a self-aligned silicide technique is provided. The method includes forming a gate electrode and a silicidation resistant layer pattern that are sequentially stacked on a predetermined region of a semiconductor substrate. Impurities are implanted into the semiconductor substrate to form a source/drain region. A first metal silicide layer is selectively formed on the surface of the source/drain region. The silicidation resistant layer pattern is then removed to expose the gate electrode. A second metal silicide layer is selectively formed on the exposed gate electrode. Consequently, the first metal silicide layer can be formed of a metal silicide layer having superior tolerance with respect to junction spiking. Also, the second metal silicide layer can be formed of another metal silicide layer having a low variation of resistivity due to the variation of the line width of the gate electrode. Therefore, it is possible to fabricate a high-performance MOS transistor suitable for a highly integrated semiconductor device.

Claims16

Dependent claims

A method for fabricating a MOS transistor comprising:

forming a gate pattern including a gate electrode and a silicidation resistant layer sequentially stacked on a semiconductor substrate;
conformally forming a screen oxide layer over the semiconductor substrate including the gate pattern;
implanting impurities into the semiconductor substrate using the gate pattern as an ion-implantation mask to form a low concentration source/drain region;
forming an insulation spacer on a sidewall of the gate pattern;
implanting impurities into the semiconductor substrate using the gate pattern and the insulation spacer as ion-implantation masks to form a high concentration source/drain region having an impurity concentration that is higher than that of the low concentration source/drain region;
selectively forming a first metal silicide layer on a surface of the high concentration source/drain region;
removing the silicidation resistant layer pattern to expose the gate electrode;
and
selectively forming a second metal silicide layer on a surface of the exposed gate electrode.

6 more elements

Dependencies are inferred from the claim text.

Method for fabricating a MOS transistor using a self-aligned silicide technique

Life of this patent

Method for fabricating a MOS transistor using a self-aligned silicide technique

Life of this patent

Abstract

Claims16