Method of manufacturing non-volatile semiconductor memory device

A method of fabricating a non-volatile semiconductor memory device, comprising:

• forming a control gate on a portion of a memory cell area of a semiconductor substrate, wherein the memory cell area, which is divided into a first region and a second region by the control gate, is defined by a device isolation layer;
• inserting a control gate insulating layer between the control gate and the semiconductor substrate;
• forming a first insulating layer on an exposed surface of the control gate;
• forming a second insulating layer on a surface of the first insulating layer at a side of the control gate, wherein the etch selectivity of the second insulating layer differs from the etch selectivity of the first insulating layer;
• forming a drain region in the first region adjacent the control gate;
• forming a tunneling oxide layer on an exposed surface of the first region and the second region of the substrate;
• forming a conductive layer over the substrate including the tunneling oxide layer, and the first insulating layer;
• forming a source region in the second region;
• and
• forming a floating gate and a third insulating layer by patterning the conductive layer, wherein the floating gate overlaps a large portion of the drain region and a small portion of the source region.