Methods of forming gated semiconductor assemblies
AssigneeMicron Technology, Inc.
InventorsMark A. Helm, Mark Fischer, John T. Moore, Scott Jeffrey DeBoer
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AssigneeMicron Technology, Inc.
InventorsMark A. Helm, Mark Fischer, John T. Moore, Scott Jeffrey DeBoer
Estimating the term…
The invention includes a method of forming a gated semiconductor assembly. A first transistor gate layer is formed over a substrate. A silicon nitride layer is formed over the first transistor gate layer. The silicon nitride layer comprises a first portion and a second portion elevationally displaced above the first portion. The first portion has less electrical resistance than the second portion and a different stoichiometric composition than the second portion. The first portion is physically against the second portion. A second transistor gate layer is formed over the silicon nitride layer.
A method of forming a gated semiconductor assembly, comprising:
A method of forming a gated semiconductor assembly, comprising:
A method of forming a semiconductor assembly, comprising:
Dependencies are inferred from the claim text.
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Floating-gate IGFETs: having only two programming levels
Characterised by the insulator, e.g. by the gate insulator: having a compositional variation, e.g. multilayered
Of data-storage electrodes: comprising conductor-insulator-conductor-insulator-semiconductor structures
Inorganic electric semiconductor devices
Term ended 7 Apr 2018 (estimated)
USPTO file history isn’t available for this patent, so only indexed dates are shown.
The invention pertains to gated semiconductor assemblies, such as, for example, erasable, programmable read-only memories (EPROMS), electrically erasable proms (EEPROMS), and flash EEPROMS.
Read-only-memories (ROMs) are memories into which information is permanently stored during fabrication. Such memories are considered “non-volatile” as only read operations can be performed.
Each bit of information in a ROM is stored by the presence or absence of a data path from the word (access) line to a bit (sense) line. The data path is eliminated simply by insuring no circuit element joins a word and bit line. Thus, when the word line of a ROM is activated, the presence of a signal on the bit line will mean that a 1 is stored, whereas the absence of a signal indicates that a 0 is stored.
Preferred embodiments of the invention are described below with reference to the following accompanying drawings.
FIG. 1 is a fragmentary, diagrammatic top view of a prior art gated semiconductor assembly
FIG. 2 is a diagrammatic, fragmentary, cross-sectional view of the FIG. 1 gated semiconductor assembly along the line X—X of FIG. 1.
This disclosure of the invention is submitted in furtherance of the constitutional purposes of the U.S. Patent Laws “to promote the progress of science and useful arts” (Article 1, Section 8).
A method of forming a gated semiconductor assembly in accordance with the present invention is described with reference to FIGS. 4-11. FIGS. 4, 6, 8 and 10 are views of a semiconductor wafer fragment shown at sequential steps of a fabrication process, and shown along an axis corresponding to line X—X of FIG. 1. FIGS. 5, 7, 9 and 11 are views of the processed wafer fragments of FIGS. 4, 6, 8 and 10, respectively, along an axis corresponding to line Y—Y of FIG. 1.
Referring to FIGS. 4 and 5, a semiconductor wafer fragment 40 comprises a substrate 42, and field oxide regions 44 formed over substrate 42. Substrate 42 and field oxide regions 44 can comprise the same compositions as substrate 12 and field oxide regions 14 discussed above in the “background” section. A portion of substrate 42 between field oxide regions 44 is defined as an active region.