Method to reduce lot-to-lot variation of array threshold voltage in a DRAM device

A method to reduce variation of an output parameter by selection of an optimal process recipe in the manufacture of an integrated circuit device comprising:

• measuring an integrated circuit device wafer to obtain a present set of process parameter values;
• thereafter calculating a predicted value of an output parameter by evaluating a first equation at said present set of process parameter values wherein said first equation is derived from a plurality of previous sets of process parameter values and the corresponding plurality of sets of output parameter values, wherein said first equation is of the form:
• OPpredicted=X0+X1(P1M−P1T)+X2(P2M−P2T)+ . . . +Xn(PnM−PnT),
• and wherein OPpredicted is said predicted value of output parameter, X0 through Xn are derived constants, P1M through PnM are said present set of process parameter values, and P1T through PnT are the target values for said set of process parameters;
• thereafter calculating an output parameter delta wherein said output parameter delta is the difference between said predicted value of said output parameter and a target value of said output parameter;
• thereafter calculating a process recipe offset by evaluating a second equation at said output parameter delta wherein said second equation is derived from the plurality of selectable process recipes and the plurality of corresponding output parameter values, wherein said second equation is of the form:
• ΔPR=Y(ΔOP), and wherein ΔPR is said process recipe offset, Y is a derived constant, and ΔOP is said output parameter delta;
• and
• selecting an optimal process recipe from said plurality of selectable process recipes by adding said process recipe offset to a target process recipe to thereby reduce the variation of said output parameter in the manufacture of the integrated circuit device.

A method to reduce variation of the array threshold voltage (Vt) of a DRAM circuit by selection of an optimal process recipe in the manufacture of an integrated circuit device comprising:

• measuring an integrated circuit device wafer to obtain a present set of process parameter values;
• thereafter calculating a predicted value of the array threshold voltage (Vt) by evaluating a first equation at said present set of process parameter values wherein said first equation is derived from a plurality of previous sets of process parameter values and the corresponding plurality of sets of the array threshold voltage (Vt), wherein said first equation is of the form:
• VTpredicted=X0+X1(P1M−P1T)+X2(P2M−P2T)+ . . . +Xn(PnM−PnT), and wherein VTpredicted is said predicted value of said array threshold voltage (Vt), X0 through Xn are derived constants, P1M through PnM are said present set of process parameter values, and P1T through PnT are the target values for said set of process parameters;
• thereafter calculating an array threshold voltage (Vt) delta wherein said array threshold voltage (Vt) delta is the difference between said predicted value of said array threshold voltage (Vt) and a target value of said array threshold voltage (Vt);
• thereafter calculating a source/drain ion implantation recipe offset by evaluating a second equation at said array threshold voltage (Vt) delta wherein said second equation is derived from the plurality of selectable source/drain ion implantation recipes and the plurality of corresponding array threshold voltage (Vt) values, wherein said second equation is of the form:
• ΔPR=Y(ΔVT), and wherein ΔPR is said source/drain ion implantation recipe offset, Y is a derived constant, and ΔVT is said array threshold voltage (Vt) delta;
• and
• selecting an optimal source/drain ion implantation recipe from said plurality of selectable source/drain ion implantation recipes by adding said source/drain ion implantation recipe offset to a target source/drain ion implantation recipe to thereby reduce the variation of said array threshold voltage (Vt) in the manufacture of the integrated circuit device.