Device and method for limiting the extent to which circuits in integrated circuit dice electrically load bond pads and other circuit nodes in the dice

An integrated circuit die comprising:

• a plurality of terminals for communicating with circuitry external to said integrated circuit die;
• a plurality of load circuits for electrically loading said plurality of terminals for having at least one terminal of said plurality of terminals loaded with more load circuits of said plurality of load circuits than other terminals of said plurality of terminals;
• and
• a plurality of programmable circuits, each programmable circuit coupled between said at least one terminal loaded with more load circuits of said plurality of load circuits and a corresponding one of said plurality of load circuits capable of loading said at least one terminal, said plurality of programmable circuits for isolating said at least one terminal from at least one other load circuit of said plurality of load circuits for loading said at least one terminal for reducing an electrical load in said at least one terminal to be substantially the same as an electrical load in remaining terminals of said plurality of terminals, said plurality of programmable circuits including at least one of a fuse and an anti-fuse.

An integrated circuit die comprising:

• a plurality of terminals for communicating with circuitry external to said integrated circuit die;
• a plurality of load circuits for electrically loading said plurality of terminals for having at least one terminal of said plurality of terminals loaded with more of said plurality of load circuits than at least one remaining terminal of said plurality of terminals;
• and
• a plurality of programmable circuits, each programmable circuit coupled between said at least one terminal loaded with more of said plurality of load circuits and a corresponding one of said plurality of load circuits capable of loading said at least one terminal, said plurality of programmable circuits for isolating said at least one terminal from at least one load circuit of said plurality of load circuits for loading said at least one terminal for reducing an electrical load in said at least one terminal to be substantially the same as an electrical load in at least one of remaining terminals of said plurality, said plurality of programmable circuits including at least one of a fuse and an anti-fuse.

A semiconductor wafer comprising at least one semiconductor die thereon, said at least one semiconductor die having at least one circuit, comprising:

• a plurality of terminals for communication with circuitry external to said at least one semiconductor die;
• a plurality of load circuits for electrically loading said plurality of terminals such that at least one terminal of said plurality of terminals is loaded with more load circuits of said plurality of load circuits than at least one other terminal of said plurality of terminals;
• and
• a plurality of programmable circuits, each programmable circuit coupled between said at least one terminal of said plurality of terminals for loading with more of said plurality of load circuits and a corresponding one of said plurality of load circuits constructed to load said at least one terminal, said plurality of programmable circuits for isolating said at least one terminal from at least one other load circuit of said plurality of load circuits constructed for loading said at least one terminal for reducing an electrical load in said at least one terminal to be substantially the same as an electrical load in remaining terminals of said plurality of terminals, said plurality of programmable circuits including at least one of a fuse and an anti-fuse.

An electronic system comprising an input device, an output device, a memory device, and a processor device coupled to said input, output, and memory devices, at least one of said input, output, memory, and processor devices comprising a semiconductor die having at least one circuit therein comprising:

• a plurality of terminals for communicating with circuitry external to said semiconductor die, said plurality of terminals including a first terminal;
• a plurality of load circuits for electrically loading said plurality of terminals, including said first terminal;
• and
• a plurality of programmable circuits, each programmable circuit coupled between said first terminal and a corresponding one of said plurality of load circuits for loading said first terminal, said plurality of programmable circuits for isolating said first terminal from at least some of said plurality of load circuits constructed to load said first terminal for reducing an electrical load in said first terminal to be substantially the same as an electrical load in remaining terminals of said plurality of terminals, said plurality of programmable circuits including one of a fuse and an anti-fuse.

A semiconductor die having an active surface comprising:

• a plurality of bond pads located on said active surface;
• a plurality of first load circuits for communicating through said plurality of bond pads in a first operating mode of said semiconductor die having each first load circuit of said plurality electrically loading its respective bond pad with substantially the same electrical load;
• a second load circuit for communicating through one of said plurality of bond pads in a second operating mode of said semiconductor die having said second load circuit electrically loading its respective bond pad with an additional electrical load such that its respective bond pad has more of an electrical load than remaining bond pads;
• a first fuse interposed between said respective bond pad associated with said second load circuit and each first load circuit for coupling said respective bond pad to each first load circuit in said first operating mode and for isolating said respective bond pad from each first load circuit in said second operating mode;
• and
• a second fuse interposed between said respective bond pad associated with said second load circuit and said second load circuit for coupling said respective bond pad to said second load circuit in said second operating mode and for isolating said respective bond pad from said second load circuit in said first operating mode for reducing said electrical load on said respective bond pad to be substantially the same as said electrical load in said remaining bond pads.