Method of predicting lifetime of semiconductor integrated circuit and method for reliability testing of the circuit
AssigneeMatsushita Electric Industrial Co., Ltd.
InventorKenji Okada
Life of this patent
Estimating the term…
Abstract
A time it takes for a total leakage current (i.e., a total amount of B-mode stress induced leakage currents) flowing through respective MOS devices in a semiconductor integrated circuit to reach a predetermined reference level is estimated as an expected lifetime of the circuit.
Claims7
A method of predicting the lifetime of a semiconductor integrated circuit, characterized by comprising:
- a first step of deriving, as a unit leakage current level, the amount of a B-mode stress induced leakage current flowing through each of SBD spots where a soft breakdown has occurred in multiple MOS devices included in the circuit;
- a second step of obtaining a critical spot number from the unit leakage current level, the critical spot number being a minimum number of SBD spots required for a total amount of B-mode stress induced leakage currents, flowing through the respective MOS devices, to exceed a predetermined reference level;
- and
- a third step of estimating, as an expected lifetime of the circuit, a time it takes for the number of SBD spots in the MOS devices to reach the critical spot number.
A method for reliability testing of a semiconductor integrated circuit, characterized by comprising:
- a first step of estimating a first time it takes for a total amount of B-mode stress induced leakage currents, flowing through respective MOS devices in the circuit, to reach a predetermined reference level where an actual operating voltage is applied to the circuit;
- a second step of estimating a second time it takes for an MOS device under test to cause a soft breakdown from the first time where a test voltage, higher than the actual operating voltage, is applied thereto, and then determining, by the second time, a reference control level for a predetermined control point of the device under test;
- and
- a third step of measuring the control point of the device under test where the test voltage is applied thereto, and then determining whether or not a result of the measurement meets the reference control level.
A method of predicting the lifetime of a semiconductor integrated circuit, characterized by estimating, as an expected lifetime of the circuit, a time it takes for a total amount of B-mode stress induced leakage currents, flowing through respective MOS devices in the circuit, to reach a predetermined reference level.
Dependencies are inferred from the claim text.