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US 6,633,083 B2Granted
Barrier layer integrity test
AssigneeAdvanced Micro Devices, Inc.
InventorsChristy Mei-Chu Woo, Young-Chang Joo, Todd Lukanc
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Abstract
A structure and method for determining barrier layer integrity for multi-level copper metallization structures in integrated circuit manufacturing. Novel testing structures prevent any conducting residues of the copper CMP from diffusing into the dielectric layer. Barrier layer integrity is tested by performing CV or IV measurements between the copper lines and the silicon wafer.
Claims20
A structure for testing the integrity of a barrier layer underlying copper lines in a Cu metallization structure comprising:
- a semiconductor substrate, said semiconductor substrate having a back surface;
- a dielectric layer on said semiconductor substrate, said dielectric layer having a Damascene line region etched therein, said Damascene line region having a bottom surface and side surfaces, said dielectric layer having a top surface;
- a barrier layer, said barrier layer being composed of a barrier layer material, said barrier layer being on said bottom and said side surfaces of said Damascene line region and filling a first portion of said Damascene line region, a remaining portion of said Damascene line region not being filled with said barrier layer;
- said remaining portion of said Damascene line region filled with copper, said copper having a top surface;
- a first cap layer, said first cap layer being contiguously atop said top surface of said copper and being atop said top surface of said dielectric layer;
- a copper diffusion inhibitor layer having sufficiently low permeability to copper diffusion to inhibit copper from diffusing therethrough, said copper diffusion inhibitor layer being contiguous to and atop said top surface of said dielectric layer, said copper diffusion inhibitor layer also being contiguous to and below said first cap layer;
- said copper diffusion inhibitor layer abutting said barrier layer on said side surfaces of said Damascene line region, and said copper diffusion inhibitor layer being removed from atop said copper;
- a first electrical contact to said top surface of said copper and a second electrical contact to said back surface of said semiconductor substrate for enabling electrical characteristic measurement between said first and second electrical contacts indicative of integrity of said barrier layer;
- said copper diffusion inhibitor layer being comprised of a material selected from the group consisting of:
- Ta, CVD Ta, CVD Ti, CVD TiN, CVD TaN, CVD WN, CVD WSiN, CVD TaSiN, CVD TiSiN, PVD Ta, PVD Ti, PVD TiN, PVD TaN, PVD WN, PVD WSiN, PVD TaSiN, PVD TiSiN, and combinations thereof, and silicon nitride.
7 more elements
A structure for testing the integrity of a barrier layer underlying copper lines in a Cu metallization structure comprising:
- a semiconductor substrate, said semiconductor substrate having a back surface;
- a dielectric layer on said semiconductor substrate, said dielectric layer having a Damascene line region etched therein, said Damascene line region having a bottom surface and side surfaces, said dielectric layer having a top surface;
- a barrier layer, said barrier layer being composed of a barrier layer material, said barrier layer being on said bottom and said side surfaces of said Damascene line region and filling a first portion of said Damascene line region, a remaining portion of said Damascene line region not being filled with said barrier layer;
- said remaining portion of said Damascene line region filled with copper, said copper having a top surface;
- a first cap layer, said first cap layer being contiguously atop said top surface of said copper and being atop said top surface of said dielectric layer;
- a copper diffusion inhibitor layer having sufficiently low permeability to copper diffusion to inhibit copper from diffusing therethrough, said copper diffusion inhibitor layer being contiguous to and atop said top surface of said dielectric layer, said copper diffusion inhibitor layer also being contiguous to and below said first cap layer;
- said copper diffusion inhibitor layer abutting said barrier layer on said side surfaces of said Damascene line region, and said copper diffusion inhibitor layer being removed from atop said copper;
- a first electrical contact to said top surface of said copper and a second electrical contact to said back surface of said semiconductor substrate for enabling electrical characteristic measurement between said first and second electrical contacts indicative of integrity of said barrier layer;
- wherein said dielectric layer includes a first portion underlying said Damascene line region and a second portion not underlying said Damascene line region, and wherein said second portion not underlying said Damascene line region includes a first dielectric layer, an etch stop layer atop said first dielectric layer, and a second dielectric layer atop said etch stop layer.
6 more elements
A structure for testing the integrity of a barrier layer underlying copper lines in a Cu metallization structure comprising:
- a semiconductor substrate, said semiconductor substrate having a back surface;
- a dielectric layer on said semiconductor substrate, said dielectric layer having a Damascene line region etched therein, said Damascene line region having a bottom surface and side surfaces, said dielectric layer having a top surface;
- a barrier layer, said barrier layer being composed of a barrier layer material, said barrier layer being on said bottom and said side surfaces of said Damascene line region and filling a first portion of said Damascene line region, a remaining portion of said Damascene line region not being filled with said barrier layer;
- said remaining portion of said Damascene line region filled with copper, said copper having a top surface;
- a first cap layer, said first cap layer being contiguously atop said top surface of said copper and being atop said top surface of said dielectric layer;
- a copper diffusion inhibitor layer having sufficiently low permeability to copper diffusion to inhibit copper from diffusing therethrough, said copper diffusion inhibitor layer being contiguous to and atop said top surface of said dielectric layer, said copper diffusion inhibitor layer also being contiguous to and below said first cap layer;
- said copper diffusion inhibitor layer abutting said barrier layer on said side surfaces of said Damascene line region, and said copper diffusion inhibitor layer being removed from atop said copper;
- a first electrical contact to said top surface of said copper and a second electrical contact to said back surface of said semiconductor substrate for enabling electrical characteristic measurement between said first and second electrical contacts indicative of integrity of said barrier layer;
- wherein said electrical contact to said back surface of said semiconductor substrate comprises a metal layer on said back surface of said substrate and an electrical contact to said metal layer.
6 more elements
A structure for testing the integrity of a barrier layer underlying copper lines in a Cu metallization structure comprising:
- a semiconductor substrate, said semiconductor substrate having a back surface;
- a dielectric layer on said semiconductor substrate, said dielectric layer having a Damascene line region etched therein, said Damascene line region having a bottom surface and side surfaces, said dielectric layer having a top surface;
- a barrier layer, said barrier layer being composed of a barrier layer material, said barrier layer being on said bottom and said side surfaces of said Damascene line region and filling a first portion of said Damascene line region, a remaining portion of said Damascene line region not being filled with said barrier layer;
- said remaining portion of said Damascene line region filled with copper, said copper having a top surface;
- a first cap layer, said first cap layer being contiguously atop said top surface of said copper and being atop said top surface of said dielectric layer;
- a copper diffusion inhibitor layer having sufficiently low permeability to copper diffusion to inhibit copper from diffusing therethrough, said copper diffusion inhibitor layer being contiguous to and atop said top surface of said dielectric layer, said copper diffusion inhibitor layer also being contiguous to and below said first cap layer;
- said copper diffusion inhibitor layer abutting said barrier layer on said side surfaces of said Damascene line region, and said copper diffusion inhibitor layer being removed from atop said copper;
- a first electrical contact to said top surface of said copper and a second electrical contact to said back surface of said semiconductor substrate for enabling electrical characteristic measurement between said first and second electrical contacts indicative of integrity of said barrier layer;
- wherein said copper diffusion inhibitor layer comprises a second cap layer, said second cap layer abutting and being contiguous with said first barrier layer portion on said side surfaces of said Damascene region, said second cap layer being removed from atop said copper, said second cap layer and said copper having said barrier layer on said side surfaces of said Damascene region disposed therebetween.
6 more elements
Dependencies are inferred from the claim text.