Contact structure for a ferroelectric memory device

A ferroelectric memory device, comprising:

• a matrix array of ferroelectric memory cells integrated in a semiconductor substrate and arrayed as a plurality of rows and columns, wherein each cell includes a MOS device and a ferroelectric capacitor connected to each other;
• said MOS device having first and second conduction terminals and being covered with an insulating layer;
• said ferroelectric capacitor having a lower plate formed on said insulating layer above said first conduction terminals and connected electrically to said terminals, said lower plate being covered with a layer of a ferroelectric material and coupled capacitively to an upper plate;
• and
• a first plurality of plugs filled with a non-conductive material and positioned between said first conduction terminals and said ferroelectric capacitor, and a second plurality of plugs filled with a conductive material and coupled to said second conduction terminals or said control circuitry.

A ferroelectric memory cell comprising:

• a MOS transistor having first and second terminals;
• a first contact region formed in a first contact opening having an interior surface, the first contact region including a barrier layer of conductive material coating the interior surface of the first contact opening and contacting the first terminal, the first contact opening being filled with a non-conductive plug;
• and
• a second contact region formed in a second contact opening having an interior surface, the second contact region including a barrier layer of conductive material coating the interior surface of the second contact opening and contacting the second terminal, the second contact opening being filled with a conductive plug;
• a ferroelectric capacitor having first and second plates wherein the first plate is electrically connected to one of the first and second contact regions and the second plate is capacitively coupled to the first plate.