Method of forming almost L-shaped spacer for improved ILD gap fill

A method for the creation of gate spacers over sidewalls of a patterned and etched layer of gate material, comprising the steps of:

• providing a semiconductor substrate, said substrate having been provided with active surface regions in the surface thereof;
• creating at least one .patterned and etched layer of gate electrode material over the active surface regions of said substrate;
• providing impurity implantations into the active surface regions of said substrate self-aligned with sand at least one patterned and etched layer of gate electrode material;
• creating a layer of liner oxide over exposed surfaces of said at least one patterned and etched layer of gate electrode material, thereby including the surface of said active surface regions provided in the surface of said substrate;
• creating gate spacers of silicon nitride offer sidewalls of said at least one patterned and etched layer of gate electrode material;
• depositing a layer of TEOS over the exposed surface of said gate spacers, thereby including exposed surfaces of said layer of liner oxide;
• depositing a layer of silicon nitride over the surface of said layer of TEOS;
• etching said layer of silicon nitride, stopping on about the surface of said layer of TECS, thereby reducing an original thickness of said layer of TEOS by a ,measurable amount;
• then
• over-etching through the layer of TEOS deposited over the exposed surface of said gate spacers, creating an opening through the layer of TEOS where the layer of TEOS overlies the gate spacers, exposing the surface of said gate spacers, forming stringers of TEOS adjacent to said opening created through the layer of TEOS and overlying the gate spacers;
• and etching the exposed surface of said gate spacers.

A method for the creation of gate spacers over sidewalls of a patterned and etched layer of gate material, comprising the steps of:

• (A) providing a semiconductor substrate, said substrate having been provided with active surface regions in the surface thereof;
• (B) creating at least one patterned and etched layer of gate electrode material over the active surface regions of said substrate;
• (C) providing impurity implantations into the active surface regions of said substrate self-aligned with said at least one patterned and etched layer of gate electrode material;
• (D) creating a layer of liner oxide over exposed surfaces of said at least one patterned and etched layer of gate electrode material, thereby including the surface of said active surface regions provided in the surface of said substrate;
• (E) creating gate spacers using a layer of gate spacer material over sidewalls of said at least one patterned and etched layer of gate electrode material;
• (F) depositing a layer of high-temperature imageable material over the exposed surface of said gate spacers, thereby including exposed surfaces of said layer of liner oxide, said layer of high-temperature imageable material being selected as having an etch rate that is lower than an etch rate of said layer of gate spacer material by a measurable amount, said layer of high-temperature imageable material further being selected as being able to combine with said layer of liner oxide forming a combined layer having uniform semiconductor processing characteristics of said combined layer;
• (G) etching said layer of high-temperature imageable material, said etching comprising:
• (i) stopping on about the surface of said layer of gate spacer material, creating an opening through the layer of high-temperature imageable material where the layer of high-temperature imageable material overlies the gate spacers, exposing the surface of said gate spacers;
• and
• (ii) forming stringers of high-temperature imageable material adjacent to said opening created through the layer of high-temperature imageable material and overlying the gate spacers;
• and
• (H) etching the exposed surface of said gate spacers.

A method for the creation of gate spacers over sidewalls of a patterned and etched layer of gate material, comprising the steps or:

• providing a semiconductor substrate, said substrate having been provided with active surface regions in the surface thereof;
• creating at least one patterned and etched layer of gate electrode material over the active surface regions of said substrate;
• providing impurity implantations into the active surface regions of said substrate self-aligned with said at least one patterned and etched layer of gate electrode material;
• creating a layer of liner oxide over exposed surfaces of said at least ore patterned and etched layer of gate electrode material, thereby including the surface of said active surface regions provided in the surface of said substrate;
• creating gate spacers of silicon nitride over sidewalls of said at least one patterned and etched layer of gate electrode material;
• depositing a layer of TEOS over exposed surface of said gate spacers, thereby including exposed surfaces of said layer of liner oxide;
• etching said layer of TEOS, stopping on about the surface of said gate spacers, creating an opening through the layer of TEOS where the layer of TEOS overlies the gate spacers, exposing the surface of said gate spacers, forming stringers of TEOS adjacent to said opening created through the layer of TEOS and overlying the gate spacers;
• and
• etching the exposed surface of said gate spacers.