Interconnect structures containing stress adjustment cap layer

Abstract

Novel interconnect structures possessing a relatively low internal stress and dielectric constant for use in semiconductor devices are provided herein. The novel interconnect structures comprise a first layer having a coefficient of thermal expansion greater than about 20 ppm and a first internal stress associated therewith, the first layer having a first set of metallic lines formed therein; a second layer having a coefficient of thermal expansion less than about 20 ppm and a second internal stress associated therewith, the second layer having a second set of metallic lines formed therein; and one or more stress adjustment cap layers formed between the first layer and the second layer, the cap layer(s) having a third internal stress to offset the first stress of the first layer and the second stress of the second layer and inducing a favorable relief of stress on the interconnect structure. Methods for making a semiconductor device having a substantially reduced internal stress are also provided.

Dependencies are inferred from the claim text.