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US 6,617,641 B2Granted
High voltage semiconductor device capable of increasing a switching speed
AssigneeKabushiki Kaisha Toshiba
InventorsAkio Nakagawa, Tomoko Matsudai
Life of this patent
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Abstract
An IGBT has a punch-through structure including an n+ buffer layer. It includes a p− low concentration layer formed between the n+ buffer layer and a p+ drain layer. Owing to the low concentration layer, the drain current decreases to zero gradually, not rapidly, when the IGBT is turned off.
Claims32
A semiconductor device comprising:
- a drain layer of a first conductivity type;
- a buffer layer of a second conductivity type formed above the drain layer;
- a high resistance layer of the second conductivity type formed on the buffer layer;
- a base layer of the first conductivity type formed on the high resistance layer;
- a source layer of the second conductivity type, containing a high concentration of impurities, formed in a surface region of the base layer;
- a gate electrode formed in the base layer with an insulating film interposed therebetween;
- and
- a low concentration layer formed between the drain layer and the buffer layer, an impurity concentration of the low concentration layer being lower than those of the drain layer and the buffer layer,
- wherein the drain layer is an impurity diffusion layer, and a total amount of impurities contained in the drain layer is at most 5×1014 cm−2.
6 more elements
A semiconductor device comprising:
- a drain layer of a first conductivity type;
- a buffer layer of a second conductivity type formed above the drain layer;
- a high resistance layer of the second conductivity type formed on the buffer layer;
- a base layer of the first conductivity type formed on the high resistance layer;
- a source layer of the second conductivity type, containing a high concentration of impurities, formed in a surface region of the base layer;
- a gate electrode formed in the base layer with an insulating film interposed therebetween;
- and
- a drain electrode to supply a potential to the drain layer,
- a low concentration layer formed between the drain layer and the buffer layer, the low concentration layer having an impurity concentration lower than the impurity concentrations of the drain layer and the buffer layer,
- wherein a thickness of the drain layer is 1 μm or less, and a total amount of impurities contained in the drain layer is at most 5×1014 cm2.
7 more elements
A semiconductor device comprising:
- a drain layer of a first conductivity type;
- a buffer layer of a second conductivity type formed above the drain layer;
- a high resistance layer of the second conductivity type formed on the buffer layer;
- a base layer of the first conductivity type formed on the high resistance layer;
- a source layer of the second conductivity type, containing a high concentration of impurities, formed in a surface region of the base layer;
- a gate electrode formed in the base layer with an insulating film interposed therebetween;
- and
- a low concentration layer formed between the drain layer and the buffer layer, said low concentration layer having an impurity concentration lower than impurity concentrations of the drain layer and the buffer layer,
- wherein a thickness of the drain layer is 0.3 to 1 μm.
6 more elements
Dependencies are inferred from the claim text.