Ferroelectric memory device and method of fabricating the same

#This application relies for priority upon Korean Patent Application No. 2000-69282, filed on Nov. 21, 2000, the contents of which are herein incorporated by reference in their entirety.

#The present invention generally relates to a semiconductor device and a method of fabricating the semiconductor device. More specifically, the present invention is directed to a ferroelectric memory device and a method of fabricating the ferroelectric memory device.

#A ferroelectric memory device is a non-volatile memory device in which data can be stored even when power to the device is turned off. Similar to a dynamic random access memory (DRAM), a unit cell of the ferroelectric memory device is composed of one transistor and one capacitor. With an operating speed similar to that of a DRAM, the ferroelectric memory device can be highly integrated. Therefore, the ferroelectric memory device has been regarded as a next-generation non-volatile memory device.

#FIG. 1A though FIG. 1D are cross-sectional views for explaining a method of fabricating a ferroelectric memory device in accordance with a first embodiment of the present invention.

#FIG. 2 is an equivalent circuit diagram to a ferroelectric memory cell in accordance with a first embodiment of the present invention.

#FIG. 3A and FIG. 3B are cross-sectional views for explaining a method of fabricating a ferroelectric memory device in accordance with a second embodiment of the present invention.

#A new and improved ferroelectric memory device and a fabricating method thereof will now be described more fully hereinafter with reference to the accompanying drawings.

#Now, a structure of a ferroelectric memory device according to the first embodiment of the invention will be described with reference to FIG. 1D. A device isolation layer 12 is formed in a predetermined area of a semiconductor substrate 10 to define an active region. A pair of gate patterns, which are parallel with each other, i.e., first and second gate patterns 17a and 17b are formed on the top surface of the active region. A common drain region 19b is formed at an active region between the first and second gate patterns 17a and 17b. First and second source regions 19a and 19c are formed at active regions on at both sides of, and separated from the common drain region 19b, respectively. The first gate pattern 17a includes a gate oxide layer 14, a first gate electrode 15a, and a gate capping layer 16 that are sequentially stacked. Similarly, the second gate pattern 17b includes a gate oxide layer 14, a second gate electrode 15b, and a gate capping layer 16 that are sequentially stacked. The first and second gate electrodes 15a and 15b correspond to first and second wordlines, respectively. Sidewalls of the patterns 17a and 17b can be covered with spacers 20. The first gate pattern 17a, the common drain region 19b, and the first source region 19a compose a first switching element T1, i.e., a first MOS transistor. And, the second gate pattern 17b, the common drain region 19b, and the second source region 19c compose a second switching element T2, i.e., a second MOS transistor.

#A resulting structure including the first and second switching elements T1 and T2 is covered with a first interlayer insulating layer 22. A bitline 25 is located on the first interlayer insulating layer 22, and is electrically connected to the common drain region 19b through a hole penetrating a predetermined area of the first interlayer insulating layer 22. The bitline 25 and the first interlayer insulating layer 22 are covered with a second interlayer insulating layer 27. The first and second interlayer insulating layers 22 and 27 composes an interlayer insulating layer. The first source region 19a is electrically connected to a first contact plug 30a penetrating the interlayer insulating layer. And, the second source region 19c is electrically connected to a second contact plug 30b penetrating the interlayer insulating layer.