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US 6,617,620 B1Granted
Gate array with border element
AssigneeOki Electric Industry Co., Ltd.
InventorsHarumi Kawano, Katsuyoshi Takahashi
Life of this patent
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Abstract
A gate array comprises a core cell having a plurality of logic gates, a power supply pattern provided beside the core cell for providing electrical power to the core cell, and a border element provided beside the power supply pattern for providing capacitance or resistance to the core cell. The border element has a capacity cell including a transistor that provides the capacitance to the core cell, a resistor cell including a transistor that provides resistance to the core cell, and a material having resistance to be provided to the core cell.
Claims37
A gate array comprising:
- a core cell having a plurality of logic gates;
- a power supply pattern provided beside said core cell;
- and
- a border element provided beside said power supply pattern, said border element comprising at least one of,
- a capacity cell including a transistor for providing capacitance to said core cell, the capacitance of said capacity cell being larger than a capacitance of said core cell, and
- a resistor cell including a transistor for providing resistance to said core cell.
3 more elements
Dependencies are inferred from the claim text.