Method of shallow trench isolation formation and planarization
AssigneeLSI Logic Corporation
InventorsArvind Kamath, Venkatesh P. Gopinth
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Abstract
Provided is a technique for fabrication of STIs in a semiconductor device using implantation of damaging high-energy ions to insulating material overburden to generally and/or selectively increase insulation overburden removal rates. This technique avoids the use of chemical mechanical planarization (CMP) with a combination of implantation and, in some instances, low cost batch etching. The electrical characteristics of devices created with the new technique match closely to those fabricated with the standard CMP-based technique.
Claims17
A process for forming a shallow trench isolation in a semiconductor device, comprising:
- forming a pad oxide layer on the surface of a silicon substrate;
- forming an etch stop layer on the pad oxide;
- forming a shallow trench in the substrate;
- depositing an insulating fill in the trench, said insulating fill having an overburden;
- forming a mask on the insulating fill, said mask exposing regions of the overburden;
- implanting insulating fill-damaging ions into the exposed regions of the insulating fill overburden;
- removing the mask;
- and
- removing the insulating fill overburden by etch such that the regions of implanted insulator overburden are removed more rapidly than non-implanted regions under the same removal conditions.
Dependencies are inferred from the claim text.