Process of fabricating an anti-fuse for avoiding a key hole exposed

A process of fabricating an anti-fuse, comprising:

• providing a substrate;
• forming an inter-metal dielectric layer on the substrate;
• forming a first via, wherein the first via has a wide dimension at an open end thereof and a narrow dimension at a bottom end thereof and the narrow portion of the first via has a first height;
• forming a first conductive layer over the inter-metal dielectric layer and filling the first conductive layer into the first via, wherein a key hole is formed in the narrow portion of the first via;
• removing the first conductive layer outside the first via to form a conductive plug, wherein the key hole in the conductive plug is not exposed;
• performing an oxide chemical mechanical polishing process to smooth the conductive plug and removing the inter-metal dielectric layer formed in the wide portion of the first via, wherein the height of the conductive plug is approximately the same as the first height;
• covering a dielectric layer on the top side of the conductive plug;
• forming a top plate on the dielectric layer;
• forming an insulating layer over the substrate, wherein the insulating layer is provided with a second via and the second via exposes the top plate;
• and
• forming a second conductive layer over the insulating layer and filling the second conductive layer into the second via.