Quasi-damascene gate, self-aligned source/drain methods for fabricating devices
AssigneeApplied Materials, Inc.
InventorHung-Kwei Hu
Life of this patent
Estimating the term…
Abstract
Methods for use in fabricating integrated circuit structures. One embodiment of the present invention is a quasi-damascene gate, self-aligned source/drain method for forming a device on a substrate that includes steps of: (a) forming a gate dielectric layer over the substrate; (b) forming a first gate electrode layer over the gate dielectric layer; (c) forming a contact etch stop layer over the first gate electrode layer; (d) forming a self-aligning layer over the contact etch stop layer; and (e) forming and patterning a mask over the self-aligning layer.
Claims54
A quasi-damascene gate, self-aligned source/drain method for forming a device on a substrate that comprises steps of:
- forming a gate dielectric layer over the substrate;
- forming a first gate electrode layer over the gate dielectric layer;
- forming a contact etch stop layer over the first gate electrode layer;
- forming a self-aligning layer over the contact etch stop layer comprising an oxide layer;
- and
- forming and patterning a mask over the self-aligning layer.
A quasi-damascene gate, self-aligned source/drain method for forming a device on a substrate that comprises steps of:
- etching a self-aligning layer of a structure to define a gate electrode dimension, which structure comprises a substrate, a gate dielectric layer, a first gate electrode layer, an oxide contact etch stop layer and a self-aligning layer.
Dependencies are inferred from the claim text.