Method for achieving high self-aligning vertical gate studs relative to the support isolation level
AssigneeInfineon Technologies AG
InventorKlaus Hummler
Life of this patent
Estimating the term…
Abstract
A vertical gate transistor has a gate stud (14) that extends above the substrate (20) surface in order to contact a word line. The stud is formed of a first material (26) and a second material (28) having differently selective etch characteristics. The second material (18) is formed within a recess in the first material (26), and the first material (26) is then selectively etched back substantially, with the second material remaining and extending above the surrounding substrate. The gate stud (14) can then accommodate a thick array top oxide (34) and subsequent chemical mechanical polish and perform in a wide process window.
Claims12
A method of fabricating a vertical gate transistor comprising:
- forming a trench in a semiconductor substrate, the area of the trench being defined in at least one direction by a pad layer formed atop the semiconductor substrate;
- forming a gate conductor in the trench;
- forming a recess within the trench and partially filling the recess with a conformal conductive layer while leaving a first recess within the conformal conductive layer;
- at least partially filling the first recess with a second conductive layer;
- etching the conformal conductive layer to a level substantially coplanar with the pad layer;
- removing the pad layer;
- etching back the conformal conductive layer to a level below a top surface of the semiconductor substrate;
- forming a liner layer atop the semiconductor substrate, the gate conductor, and the second conductive layer.
A method of forming a vertical gate semiconductor device comprising:
- forming a patterned layer on a top surface of a semiconductor wafer, the patterned layer having openings therein defining a trench region;
- forming a trench in the trench region;
- filling the trench with a gate conductor to a level substantially coplanar with the pad layer;
- etching back the gate conductor to a level below the top surface of the semiconductor wafer;
- applying a conformal layer of first gate stud material atop the pad layer and within the deep trench;
- planarizing the conformal layer of first gate stud material to a level substantially coplanar with the pad layer;
- forming a layer of second gate stud material in a recess formed within the conformal layer of first gate stud material, the second gate stud material protruding above the level of the pad layer;
- etching back the conformal layer of first gate stud material with an etchant that does not substantially etch back the second gate stud material;
- forming a first insulator layer over the remaining conformal layer of first gate stud material and the second gate stud material;
- forming a second insulator layer over the first insulator layer;
- and
- removing the first and second insulator layer from a region on the second gate stud material to form a gate contact.
Dependencies are inferred from the claim text.